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| author | Clifford Wolf <clifford@clifford.at> | 2015-09-18 10:01:08 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-18 10:01:08 +0200 |
| commit | c89ceee219b5a6412a64f585caeceb5db9528fe4 (patch) | |
| tree | ea0a19d34feb59b343868f18a2c817ead1bcad0a | |
| parent | 7a230d3a8dd6f19ab403cc831bf57ca31fc7f3da (diff) | |
| download | yosys-c89ceee219b5a6412a64f585caeceb5db9528fe4.tar.gz yosys-c89ceee219b5a6412a64f585caeceb5db9528fe4.tar.bz2 yosys-c89ceee219b5a6412a64f585caeceb5db9528fe4.zip | |
Added $finish and $display to README
| -rw-r--r-- | README | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -367,6 +367,10 @@ Verilog Attributes and non-standard features expressions as <size>. If the expression is not a simple identifier, it must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 +- The system tasks $finish and $display are supported in initial blocks + in and unconditional context (only if/case statements on parameters + and constant values). The intended use for this is synthesis-time DRC. + Supported features from SystemVerilog ===================================== |