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| author | Stefan Biereigel <stefan@biereigel.de> | 2019-05-27 18:10:39 +0200 |
|---|---|---|
| committer | Stefan Biereigel <stefan@biereigel.de> | 2019-05-27 18:10:39 +0200 |
| commit | c5fe04acfde6e0f8c4c8f3d77a917a5918e8b839 (patch) | |
| tree | 6c1f973320014308f10e2b46e7241baba9a8f42f | |
| parent | 7f11a732102c9e5c32871de9aad2de95b20d988f (diff) | |
| download | yosys-c5fe04acfde6e0f8c4c8f3d77a917a5918e8b839.tar.gz yosys-c5fe04acfde6e0f8c4c8f3d77a917a5918e8b839.tar.bz2 yosys-c5fe04acfde6e0f8c4c8f3d77a917a5918e8b839.zip | |
remove port direction workaround from test case
| -rw-r--r-- | tests/various/wandwor.v | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/tests/various/wandwor.v b/tests/various/wandwor.v index 824f89683..d1dca6269 100644 --- a/tests/various/wandwor.v +++ b/tests/various/wandwor.v @@ -17,7 +17,6 @@ module c; wand E; - wire E_wire = E; genvar i; for (i = 0; i < 3; i = i + 1) @@ -27,7 +26,7 @@ module c; ); b b_inst ( - .D(E_wire) + .D(E) ); end |