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| author | David Shah <dave@ds0.me> | 2019-09-20 12:11:17 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-10-03 09:54:14 +0100 |
| commit | c0bb47beca2fb78670ab14515047a88a677cc608 (patch) | |
| tree | e7d4a56d30a16845be571869caf29669e2c1c3c2 | |
| parent | 497faf4ec0c078093ecef547965ae9d0fd153edb (diff) | |
| download | yosys-c0bb47beca2fb78670ab14515047a88a677cc608.tar.gz yosys-c0bb47beca2fb78670ab14515047a88a677cc608.tar.bz2 yosys-c0bb47beca2fb78670ab14515047a88a677cc608.zip | |
sv: Fix memories of typedefs
Signed-off-by: David Shah <dave@ds0.me>
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index e0a654b76..516fa4138 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1350,7 +1350,7 @@ wire_name: if ($2 != NULL) { if (node->is_input || node->is_output) frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions."); - if (!astbuf2) { + if (!astbuf2 && !node->is_custom_type) { AstNode *rng = new AstNode(AST_RANGE); rng->children.push_back(AstNode::mkconst_int(0, true)); rng->children.push_back(AstNode::mkconst_int(0, true)); |