diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:40:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:40:17 -0700 |
| commit | b810bf26ab9e40e8d7e5a5001ac3a1708309a30b (patch) | |
| tree | dbaf18493b3dd03a14a7344b3c75896156a3dd9a | |
| parent | 242b72d4e11b815d0ca4fa80eee2e112333608d2 (diff) | |
| download | yosys-b810bf26ab9e40e8d7e5a5001ac3a1708309a30b.tar.gz yosys-b810bf26ab9e40e8d7e5a5001ac3a1708309a30b.tar.bz2 yosys-b810bf26ab9e40e8d7e5a5001ac3a1708309a30b.zip | |
write_xaiger to flatten 1'bx/1'bz to 1'b0 again
| -rw-r--r-- | backends/aiger/xaiger.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 55a95d835..82f0f24b2 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -104,8 +104,10 @@ struct XAigerWriter aig_map[bit] = bit2aig(alias_map.at(bit)); } - if (bit == State::Sx || bit == State::Sz) - log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n"); + if (bit == State::Sx || bit == State::Sz) { + log_debug("Bit '%s' contains 'x' or 'z' bits. Treating as 1'b0.\n", log_signal(bit)); + aig_map[bit] = 0; + } } log_assert(aig_map.at(bit) >= 0); |