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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-04 09:09:42 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-04 09:09:42 +0100 |
| commit | b5afd75b0a8b620615bc53fa36d920760bdec46f (patch) | |
| tree | 3ca92ba762da7d2fc556da07c023552d79d655ee | |
| parent | bb20aceeb39694d089cae7dc7f493976406d4b2d (diff) | |
| download | yosys-b5afd75b0a8b620615bc53fa36d920760bdec46f.tar.gz yosys-b5afd75b0a8b620615bc53fa36d920760bdec46f.tar.bz2 yosys-b5afd75b0a8b620615bc53fa36d920760bdec46f.zip | |
Fixed gentb_constant handling in autotest backend
| -rw-r--r-- | backends/autotest/autotest.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc index 89ccc3718..3e2fab006 100644 --- a/backends/autotest/autotest.cc +++ b/backends/autotest/autotest.cc @@ -124,11 +124,11 @@ static void autotest(FILE *f, RTLIL::Design *design) is_clksignal = true; } } - if (is_clksignal && !wire->get_bool_attribute("\\gentb_constant")) { + if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) { signal_clk[idy("sig", mod->name, wire->name)] = wire->width; } else { signal_in[idy("sig", mod->name, wire->name)] = wire->width; - if (wire->get_bool_attribute("\\gentb_constant")) + if (wire->attributes.count("\\gentb_constant") != 0) signal_const[idy("sig", mod->name, wire->name)] = wire->attributes["\\gentb_constant"].as_string(); } fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str()); |