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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-11 19:24:59 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-11 19:24:59 +0200 |
| commit | b380c8c790233f9237b503656cfd28fd5e65eff5 (patch) | |
| tree | d7a717de0615f1de66c38acfc753c404a603f1f2 | |
| parent | a9fefc6ce1c0c351f88e61ec2a01ec64fc30d28f (diff) | |
| download | yosys-b380c8c790233f9237b503656cfd28fd5e65eff5.tar.gz yosys-b380c8c790233f9237b503656cfd28fd5e65eff5.tar.bz2 yosys-b380c8c790233f9237b503656cfd28fd5e65eff5.zip | |
Another vloghammer related bugfix
| -rw-r--r-- | frontends/ast/genrtlil.cc | 2 | ||||
| -rw-r--r-- | tests/simple/vloghammer.v | 7 |
2 files changed, 8 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 7a9c8ba64..791ee9867 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -836,7 +836,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_TO_SIGNED: case AST_TO_UNSIGNED: { RTLIL::SigSpec sig = children[0]->genRTLIL(); - is_signed = type == AST_TO_SIGNED; + is_signed = sign_hint; return sig; } diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v index 09987e7c9..eb0e15d02 100644 --- a/tests/simple/vloghammer.v +++ b/tests/simple/vloghammer.v @@ -50,3 +50,10 @@ module test07(a, b, y); assign y = 2'b11 != a+b; endmodule +module test08(a, b, y); + input [1:0] a; + input [1:0] b; + output y; + assign y = a == ($signed(b) >>> 1); +endmodule + |