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| author | Stefan Riesenberger <stefan.riesenberger@gmail.com> | 2021-04-09 15:44:08 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-04-09 16:46:05 +0200 |
| commit | a58571d0fe8971cb7d3a619a31b2c21be6d75bac (patch) | |
| tree | 081f6364ee2357063b77df237df3dc1b9bea6163 | |
| parent | 0b05452cf72646f74b5e148b66fc2e5a33b21207 (diff) | |
| download | yosys-a58571d0fe8971cb7d3a619a31b2c21be6d75bac.tar.gz yosys-a58571d0fe8971cb7d3a619a31b2c21be6d75bac.tar.bz2 yosys-a58571d0fe8971cb7d3a619a31b2c21be6d75bac.zip | |
sf2: fix name of AND modules
| -rw-r--r-- | techlibs/sf2/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v index eff57a655..4b57bad7b 100644 --- a/techlibs/sf2/cells_sim.v +++ b/techlibs/sf2/cells_sim.v @@ -1,20 +1,20 @@ // https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf -module ADD2 ( +module AND2 ( input A, B, output Y ); assign Y = A & B; endmodule -module ADD3 ( +module AND3 ( input A, B, C, output Y ); assign Y = A & B & C; endmodule -module ADD4 ( +module AND4 ( input A, B, C, D, output Y ); |