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author | Eddie Hung <eddie@fpgeh.com> | 2019-04-17 16:36:03 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-17 16:36:03 -0700 |
commit | a20ed260e1b12da64bc4b40682c53145f6ffe827 (patch) | |
tree | a5f5be9b52125ec1eb736e65b82c29aff48c6126 | |
parent | 709f76c10742602f5cbc0d32805a325ecab982ee (diff) | |
download | yosys-a20ed260e1b12da64bc4b40682c53145f6ffe827.tar.gz yosys-a20ed260e1b12da64bc4b40682c53145f6ffe827.tar.bz2 yosys-a20ed260e1b12da64bc4b40682c53145f6ffe827.zip |
Skip if abc_box_id earlier
-rw-r--r-- | passes/techmap/abc9.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 8b5b172ab..18f860e36 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1402,14 +1402,14 @@ struct Abc9Pass : public Pass { for (auto mod : design->selected_modules()) { + if (mod->attributes.count("\\abc_box_id")) + continue; + if (mod->processes.size() > 0) { log("Skipping module %s as it contains processes.\n", log_id(mod)); continue; } - if (mod->attributes.count("\\abc_box_id")) - continue; - assign_map.set(mod); signal_init.clear(); |