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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-13 08:22:22 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-13 08:22:22 -0700 |
| commit | 9d34cea65af5b34ce0930fb892fca6742db898ab (patch) | |
| tree | ef6ec5ce32e2059febca82b9843dc7d203e67bbd | |
| parent | c04482b07798cfcca3218cfafe0998eeb6a88f76 (diff) | |
| download | yosys-9d34cea65af5b34ce0930fb892fca6742db898ab.tar.gz yosys-9d34cea65af5b34ce0930fb892fca6742db898ab.tar.bz2 yosys-9d34cea65af5b34ce0930fb892fca6742db898ab.zip | |
More accurate CHANGELOG
| -rw-r--r-- | CHANGELOG | 4 |
1 files changed, 3 insertions, 1 deletions
@@ -17,7 +17,9 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "rename -src" - Added "equiv_opt" pass - Added "read_aiger" frontend - - Added "abc9" pass (experimental, accessible using synth_xilinx -abc9 and synth_ice40 -abc9) + - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) + - Added "synth_xilinx -abc9" (experimental) + - Added "synth_ice40 -abc9" (experimental) - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" |