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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-02 10:15:22 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-02 10:15:22 +0100 |
| commit | 990aee5531f41fdf01887870047eb924f12618b9 (patch) | |
| tree | 6cd825cb68408fcf3f41c5e48d92ad5e0480e155 | |
| parent | 169ffcd2fbd037aa1d827515af5a95a28299b832 (diff) | |
| download | yosys-990aee5531f41fdf01887870047eb924f12618b9.tar.gz yosys-990aee5531f41fdf01887870047eb924f12618b9.tar.bz2 yosys-990aee5531f41fdf01887870047eb924f12618b9.zip | |
respect hide_internal flag
| -rw-r--r-- | passes/sat/sim.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 3c8d03cba..d33c20c51 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -161,7 +161,7 @@ struct SimInstance } } - if (shared->fst) { + if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) { fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); if (id==0 && wire->name.isPublic()) log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)).c_str()); |