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author | Clifford Wolf <clifford@clifford.at> | 2014-09-06 19:44:28 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-09-06 19:44:28 +0200 |
commit | 98e6463ca78d8c0a342c9b86d9223dbeb45c093c (patch) | |
tree | ce866641e22528c52e0dbd7a5468659b476d3830 | |
parent | fa64942018a39085301d7f24832ad0ad7b0d22f1 (diff) | |
download | yosys-98e6463ca78d8c0a342c9b86d9223dbeb45c093c.tar.gz yosys-98e6463ca78d8c0a342c9b86d9223dbeb45c093c.tar.bz2 yosys-98e6463ca78d8c0a342c9b86d9223dbeb45c093c.zip |
Added $macc eval model
-rw-r--r-- | kernel/consteval.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/kernel/consteval.h b/kernel/consteval.h index c73a0b351..f995c9cc2 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -23,6 +23,7 @@ #include "kernel/rtlil.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" +#include "kernel/macc.h" struct ConstEval { @@ -210,6 +211,27 @@ struct ConstEval } } } + else if (cell->type == "$macc") + { + Macc macc; + macc.from_cell(cell); + + if (!eval(macc.bit_ports, undef, cell)) + return false; + + for (auto &port : macc.ports) { + if (!eval(port.in_a, undef, cell)) + return false; + if (!eval(port.in_b, undef, cell)) + return false; + } + + RTLIL::Const result(0, SIZE(cell->getPort("\\Y"))); + if (!macc.eval(result)) + log_abort(); + + set(cell->getPort("\\Y"), result); + } else { RTLIL::SigSpec sig_c, sig_d; |