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author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-05 21:22:41 -0800 |
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committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-05 21:22:41 -0800 |
commit | 981f01430190aeba2c27dd516cefb5730063fcc7 (patch) | |
tree | 1092800b3c19fe13c0df92ff149f0bdc84d6ce40 | |
parent | e6ab00d419ae12d7d985e2bd671bdfc74167b863 (diff) | |
download | yosys-981f01430190aeba2c27dd516cefb5730063fcc7.tar.gz yosys-981f01430190aeba2c27dd516cefb5730063fcc7.tar.bz2 yosys-981f01430190aeba2c27dd516cefb5730063fcc7.zip |
Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet.
-rw-r--r-- | techlibs/greenpak4/cells_map.v | 52 | ||||
-rw-r--r-- | techlibs/greenpak4/cells_sim.v | 68 |
2 files changed, 120 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v index 111a77a14..f8fb2569a 100644 --- a/techlibs/greenpak4/cells_map.v +++ b/techlibs/greenpak4/cells_map.v @@ -50,6 +50,58 @@ module GP_DFFRI(input D, CLK, nRST, output reg nQ); ); endmodule +module GP_DLATCHS(input D, nCLK, nSET, output reg Q); + parameter [0:0] INIT = 1'bx; + GP_DLATCHSR #( + .INIT(INIT), + .SRMODE(1'b1), + ) _TECHMAP_REPLACE_ ( + .D(D), + .nCLK(nCLK), + .nSR(nSET), + .Q(Q) + ); +endmodule + +module GP_DLATCHR(input D, nCLK, nRST, output reg Q); + parameter [0:0] INIT = 1'bx; + GP_DLATCHSR #( + .INIT(INIT), + .SRMODE(1'b0), + ) _TECHMAP_REPLACE_ ( + .D(D), + .nCLK(nCLK), + .nSR(nRST), + .Q(Q) + ); +endmodule + +module GP_DLATCHSI(input D, nCLK, nSET, output reg nQ); + parameter [0:0] INIT = 1'bx; + GP_DLATCHSRI #( + .INIT(INIT), + .SRMODE(1'b1), + ) _TECHMAP_REPLACE_ ( + .D(D), + .nCLK(nCLK), + .nSR(nSET), + .nQ(nQ) + ); +endmodule + +module GP_DLATCHRI(input D, nCLK, nRST, output reg nQ); + parameter [0:0] INIT = 1'bx; + GP_DLATCHSRI #( + .INIT(INIT), + .SRMODE(1'b0), + ) _TECHMAP_REPLACE_ ( + .D(D), + .nCLK(nCLK), + .nSR(nRST), + .nQ(nQ) + ); +endmodule + module GP_OBUFT(input IN, input OE, output OUT); GP_IOBUF _TECHMAP_REPLACE_ ( .IN(IN), diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 80746be0f..1b3a66038 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -240,6 +240,74 @@ module GP_DFFSRI(input D, CLK, nSR, output reg nQ); end endmodule +module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q); + parameter [0:0] INIT = 1'bx; + initial Q = INIT; + always @(*) begin + if(!nRST) + Q <= 1'b0; + else if(!nCLK) + Q <= D; + end +endmodule + +module GP_DLATCHRI(input D, input nCLK, input nRST, output reg Q); + parameter [0:0] INIT = 1'bx; + initial Q = INIT; + always @(*) begin + if(!nRST) + Q <= 1'b1; + else if(!nCLK) + Q <= ~D; + end +endmodule + +module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q); + parameter [0:0] INIT = 1'bx; + initial Q = INIT; + always @(*) begin + if(!nSET) + Q <= 1'b1; + else if(!nCLK) + Q <= D; + end +endmodule + +module GP_DLATCHSI(input D, input nCLK, input nSET, output reg Q); + parameter [0:0] INIT = 1'bx; + initial Q = INIT; + always @(*) begin + if(!nSET) + Q <= 1'b0; + else if(!nCLK) + Q <= ~D; + end +endmodule + +module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q); + parameter [0:0] INIT = 1'bx; + parameter[0:0] SRMODE = 1'bx; + initial Q = INIT; + always @(*) begin + if(!nSR) + Q <= SRMODE; + else if(!nCLK) + Q <= D; + end +endmodule + +module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg Q); + parameter [0:0] INIT = 1'bx; + parameter[0:0] SRMODE = 1'bx; + initial Q = INIT; + always @(*) begin + if(!nSR) + Q <= ~SRMODE; + else if(!nCLK) + Q <= ~D; + end +endmodule + module GP_EDGEDET(input IN, output reg OUT); parameter EDGE_DIRECTION = "RISING"; |