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authorClaire Xenia Wolf <claire@clairexen.net>2021-03-15 23:27:55 +0100
committerClaire Xenia Wolf <claire@clairexen.net>2021-04-20 12:46:21 +0200
commit8aee80040de0b0812f2aec7ba4059c14407a0567 (patch)
tree3828dd76be66396e43585a2681ea6d4478360edc
parentdce037a62c5bda9a8256d271d39b06be366120e8 (diff)
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Add default assignments to SB_LUT4
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
-rw-r--r--techlibs/ice40/cells_sim.v18
-rwxr-xr-xtests/arch/run-test.sh2
2 files changed, 18 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 7ee809262..2af99269c 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2,6 +2,16 @@
`define SB_DFF_REG reg Q = 0
// `define SB_DFF_REG reg Q
+`ifndef NO_ICE40_DEFAULT_ASSIGNMENTS
+`define ICE40_DEFAULT_ASSIGNMENT_V(v) = v
+`define ICE40_DEFAULT_ASSIGNMENT_0 = 1'b0
+`define ICE40_DEFAULT_ASSIGNMENT_1 = 1'b1
+`else
+`define ICE40_DEFAULT_ASSIGNMENT_V(v)
+`define ICE40_DEFAULT_ASSIGNMENT_0
+`define ICE40_DEFAULT_ASSIGNMENT_1
+`endif
+
// SiliconBlue IO Cells
module SB_IO (
@@ -164,7 +174,13 @@ endmodule
// SiliconBlue Logic Cells
(* abc9_lut=1, lib_whitebox *)
-module SB_LUT4 (output O, input I0, I1, I2, I3);
+module SB_LUT4 (
+ output O,
+ input I0 `ICE40_DEFAULT_ASSIGNMENT_0,
+ input I1 `ICE40_DEFAULT_ASSIGNMENT_0,
+ input I2 `ICE40_DEFAULT_ASSIGNMENT_0,
+ input I3 `ICE40_DEFAULT_ASSIGNMENT_0
+);
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh
index 170078a7f..5d923db56 100755
--- a/tests/arch/run-test.sh
+++ b/tests/arch/run-test.sh
@@ -11,7 +11,7 @@ for arch in ../../techlibs/*; do
if [ "${defines[$arch_name]}" ]; then
for def in ${defines[$arch_name]}; do
echo -n "Test $path -D$def ->"
- iverilog -t null -I$arch -D$def $path
+ iverilog -t null -I$arch -D$def -DNO_ICE40_DEFAULT_ASSIGNMENTS $path
echo " ok"
done
else