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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-19 21:30:46 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-19 21:30:46 +0200 |
| commit | 7ff802e199d231029f735a3e37bec508e0d840c5 (patch) | |
| tree | 73e270d11a2f68d003ed2692409d6132950a22b0 | |
| parent | 49ef830464ec03789d46595e240ff95369f21607 (diff) | |
| download | yosys-7ff802e199d231029f735a3e37bec508e0d840c5.tar.gz yosys-7ff802e199d231029f735a3e37bec508e0d840c5.tar.bz2 yosys-7ff802e199d231029f735a3e37bec508e0d840c5.zip | |
Verilog front-end: define `BLACKBOX in -lib mode
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 635c9ce47..416b89bd4 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -108,7 +108,7 @@ struct VerilogFrontend : public Frontend { log(" do not run the pre-processor\n"); log("\n"); log(" -lib\n"); - log(" only create empty blackbox modules\n"); + log(" only create empty blackbox modules. This implies -DBLACKBOX.\n"); log("\n"); log(" -noopt\n"); log(" don't perform basic optimizations (such as const folding) in the\n"); @@ -227,6 +227,7 @@ struct VerilogFrontend : public Frontend { } if (arg == "-lib") { flag_lib = true; + defines_map["BLACKBOX"] = string(); continue; } if (arg == "-noopt") { |