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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 17:29:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 17:29:45 -0700 |
| commit | 7dca8def52fdd3a0e450d3f554c328904636798d (patch) | |
| tree | c4ea7016f52694a5432a9180c0ed39a46c91ccce | |
| parent | d1dadfcec8e5fffb1d27f067a86a606591b9c686 (diff) | |
| download | yosys-7dca8def52fdd3a0e450d3f554c328904636798d.tar.gz yosys-7dca8def52fdd3a0e450d3f554c328904636798d.tar.bz2 yosys-7dca8def52fdd3a0e450d3f554c328904636798d.zip | |
Fix issue with part of PI being 1'bx
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 10 | ||||
| -rw-r--r-- | tests/simple_abc9/abc9.v | 5 |
2 files changed, 11 insertions, 4 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index b98b36319..1235af142 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -944,11 +944,13 @@ void AigerReader::post_process() if (other_wire) { other_wire->port_input = false; other_wire->port_output = false; - if (wire->port_input) - module->connect(other_wire, SigSpec(wire, i)); - else - module->connect(SigSpec(wire, i), other_wire); } + if (wire->port_input && other_wire) + module->connect(other_wire, SigSpec(wire, i)); + else + // Since we skip POs that are connected to Sx, + // re-connect them here + module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx)); } } diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 0b83c34a3..64b625efe 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -262,3 +262,8 @@ endmodule module abc9_test025(input [3:0] i, output [3:0] o); abc9_test024_sub a(i[2:1], o[2:1]); endmodule + +module abc9_test026(output [3:0] o, p); +assign o = { 1'b1, 1'bx }; +assign p = { 1'b1, 1'bx, 1'b0 }; +endmodule |