diff options
| author | gatecat <gatecat@ds0.me> | 2021-12-06 13:39:18 +0000 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2022-06-27 10:09:48 +0100 |
| commit | 7c756c9959b61160ea62b56c13c58371cb2b401c (patch) | |
| tree | b9917a0b1b279e1450156e5216cde34a384ed0dd | |
| parent | b2408df31332cdf810bc9831ae3aface1048652c (diff) | |
| download | yosys-7c756c9959b61160ea62b56c13c58371cb2b401c.tar.gz yosys-7c756c9959b61160ea62b56c13c58371cb2b401c.tar.bz2 yosys-7c756c9959b61160ea62b56c13c58371cb2b401c.zip | |
gatemate: Add preliminary sim models for LUT tree structures
Signed-off-by: gatecat <gatecat@ds0.me>
| -rw-r--r-- | techlibs/gatemate/cells_sim.v | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v index 1de3d1c7a..7e88fd7cf 100644 --- a/techlibs/gatemate/cells_sim.v +++ b/techlibs/gatemate/cells_sim.v @@ -1409,3 +1409,47 @@ module CC_BRAM_40K ( end
endgenerate
endmodule
+
+// Models of the LUT2 tree primitives
+module CC_L2T4(
+ output O,
+ input I0, I1, I2, I3
+);
+ parameter [3:0] INIT_L00 = 4'b0000;
+ parameter [3:0] INIT_L01 = 4'b0000;
+ parameter [3:0] INIT_L10 = 4'b0000;
+
+ wire [1:0] l00_s1 = I1 ? INIT_L00[3:2] : INIT_L00[1:0];
+ wire l00 = I0 ? l00_s1[1] : l00_s1[0];
+
+ wire [1:0] l01_s1 = I3 ? INIT_L01[3:2] : INIT_L01[1:0];
+ wire l01 = I2 ? l01_s1[1] : l01_s1[0];
+
+ wire [1:0] l10_s1 = l01 ? INIT_L10[3:2] : INIT_L10[1:0];
+ assign O = l00 ? l10_s1[1] : l10_s1[0];
+
+endmodule
+
+
+module CC_L2T5(
+ output O,
+ input I0, I1, I2, I3, I4
+);
+ parameter [3:0] INIT_L02 = 4'b0000;
+ parameter [3:0] INIT_L03 = 4'b0000;
+ parameter [3:0] INIT_L11 = 4'b0000;
+ parameter [3:0] INIT_L20 = 4'b0000;
+
+ wire [1:0] l02_s1 = I1 ? INIT_L02[3:2] : INIT_L02[1:0];
+ wire l02 = I0 ? l02_s1[1] : l02_s1[0];
+
+ wire [1:0] l03_s1 = I3 ? INIT_L03[3:2] : INIT_L03[1:0];
+ wire l03 = I2 ? l03_s1[1] : l03_s1[0];
+
+ wire [1:0] l11_s1 = l03 ? INIT_L11[3:2] : INIT_L11[1:0];
+ wire l11 = l02 ? l11_s1[1] : l11_s1[0];
+
+ wire [1:0] l20_s1 = l11 ? INIT_L20[3:2] : INIT_L20[1:0];
+ assign O = I4 ? l20_s1[1] : l20_s1[0];
+
+endmodule
|