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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-03 14:25:04 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-03 14:28:22 -0700 |
| commit | 7b38cde2df0631aac0377cd155653ae0e0084ed0 (patch) | |
| tree | af46b5c2be9370c224007b829c819667671c5d5c | |
| parent | 7b09a20c0cc737c3d108c9e981f5989d2ba1423c (diff) | |
| download | yosys-7b38cde2df0631aac0377cd155653ae0e0084ed0.tar.gz yosys-7b38cde2df0631aac0377cd155653ae0e0084ed0.tar.bz2 yosys-7b38cde2df0631aac0377cd155653ae0e0084ed0.zip | |
cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmp
| -rw-r--r-- | techlibs/common/cmp2lcu.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/cmp2lcu.v b/techlibs/common/cmp2lcu.v index b4fadaaad..b6f4aeed6 100644 --- a/techlibs/common/cmp2lcu.v +++ b/techlibs/common/cmp2lcu.v @@ -4,7 +4,7 @@ // which is typically mapped to dedicated (and fast) FPGA // carry-chains. (* techmap_celltype = "$lt $le $gt $ge" *) -module _90_lcu_cmp_ (A, B, Y); +module _80_lcu_cmp_ (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; |