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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-27 12:22:05 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-27 12:22:05 -0700 |
| commit | 75bd41eaeb43ec7a25f0b27ff0cdf3be361446f1 (patch) | |
| tree | fbfcefe558af577857eb4155dfc897319f14ef2d | |
| parent | bf3b8d5e45771a543c2481dee5b1b3a9aba0881e (diff) | |
| download | yosys-75bd41eaeb43ec7a25f0b27ff0cdf3be361446f1.tar.gz yosys-75bd41eaeb43ec7a25f0b27ff0cdf3be361446f1.tar.bz2 yosys-75bd41eaeb43ec7a25f0b27ff0cdf3be361446f1.zip | |
Parse without wideports
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index acbab959e..a2948548d 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -538,7 +538,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode); buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym"); log_assert(!design->module("$__abc9__")); - AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */); + AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */); reader.parse_xaiger(); ifs.close(); |