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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-13 17:07:18 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-13 17:07:18 -0700 |
| commit | 681be20ca219fc64e2bf0f9d2c24937f98903455 (patch) | |
| tree | c1805951d17067ffac6c69b9ece5e8c69de40ec3 | |
| parent | 61877e13704405a93a7ec70d0d7158f24fcafb82 (diff) | |
| download | yosys-681be20ca219fc64e2bf0f9d2c24937f98903455.tar.gz yosys-681be20ca219fc64e2bf0f9d2c24937f98903455.tar.bz2 yosys-681be20ca219fc64e2bf0f9d2c24937f98903455.zip | |
Add `undef DSP48E1_INST
| -rw-r--r-- | techlibs/xilinx/abc_map.v | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 6e36417e2..31fd79861 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -207,7 +207,7 @@ module DSP48E1 ( parameter _TECHMAP_CELLTYPE_ = ""; localparam techmap_guard = (_TECHMAP_CELLTYPE_ != ""); -`define DSP48E1_inst(__CELL__) """ +`define DSP48E1_INST(__CELL__) """ __CELL__ #( .ACASCREG(ACASCREG), .ADREG(ADREG), @@ -336,7 +336,7 @@ __CELL__ #( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_inst(\$__ABC_DSP48E1_MULT ) + `DSP48E1_INST(\$__ABC_DSP48E1_MULT ) end else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin wire [29:0] iA; @@ -381,7 +381,7 @@ __CELL__ #( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_inst(\$__ABC_DSP48E1_MULTD_PORT ) + `DSP48E1_INST(\$__ABC_DSP48E1_MULTD_PORT ) end else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin wire [29:0] iA; @@ -422,9 +422,10 @@ __CELL__ #( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_inst(\$__ABC_DSP48E1_MULTD_PORT ) + `DSP48E1_INST(\$__ABC_DSP48E1_MULTD_PORT ) end else $error("Invalid DSP48E1 configuration"); endgenerate + `undef DSP48E1_INST endmodule |