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author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-03 22:03:04 -0700 |
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committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-03 22:03:04 -0700 |
commit | 66095153fd6110dbe84552175d4919f4f5fd75fc (patch) | |
tree | b5fe378720cd68bb3dd134ffeb73d2889077c9f3 | |
parent | 9fc9d5f1fb1eea47118c00ecad1352ec84fd3047 (diff) | |
download | yosys-66095153fd6110dbe84552175d4919f4f5fd75fc.tar.gz yosys-66095153fd6110dbe84552175d4919f4f5fd75fc.tar.bz2 yosys-66095153fd6110dbe84552175d4919f4f5fd75fc.zip |
Added GreenPak I/O buffer cells
-rw-r--r-- | techlibs/greenpak4/cells_sim.v | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 7555a7ac8..a8bb538c4 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -134,6 +134,15 @@ module GP_DFFSR(input D, CLK, nSR, output reg Q); end endmodule +module GP_IBUF(input IN, output OUT); + assign OUT = IN; +endmodule + +module GP_IOBUF(input IN, input DIR, output OUT, inout IO); + assign IN = IO; + assign DIR = OE ? OUT : 1'bz; +endmodule + module GP_INV(input IN, output OUT); assign OUT = ~IN; endmodule @@ -161,6 +170,14 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT); endmodule +module GP_OBUF(input IN, output OUT); + assign OUT = IN; +endmodule + +module GP_OBUFT(input IN, input OE, output OUT); + assign OUT = OE ? IN : 1'bz; +endmodule + module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT); parameter GAIN = 1; |