diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-09-02 23:21:59 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-02 23:21:59 +0200 |
| commit | 635b922afeabea8c69ac4e749881b10aeda7448b (patch) | |
| tree | bce3fc8ace4bd5f0bc40c429ec38b8bd1e097af6 | |
| parent | f1869667cac35e897c0531c05074f3c77bfa5db9 (diff) | |
| download | yosys-635b922afeabea8c69ac4e749881b10aeda7448b.tar.gz yosys-635b922afeabea8c69ac4e749881b10aeda7448b.tar.bz2 yosys-635b922afeabea8c69ac4e749881b10aeda7448b.zip | |
Undef-related fixes in simlib $alu model
| -rw-r--r-- | techlibs/common/simlib.v | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 09ffa9a68..61215f59e 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -492,8 +492,11 @@ generate end endgenerate +// this is 'x' if Y and CO should be all 'x', and '0' otherwise +wire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI}; + assign X = AA ^ BB; -assign Y = AA + BB + CI; +assign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}}; function get_carry; input a, b, c; @@ -502,9 +505,9 @@ endfunction genvar i; generate - assign CO[0] = get_carry(AA[0], BB[0], CI); + assign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef; for (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3 - assign CO[i] = get_carry(AA[i], BB[i], CO[i-1]); + assign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef; end endgenerate |