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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-09 15:59:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-09 15:59:10 -0700 |
| commit | 5f8f0e13833ef052adb4d2d3deb8e965734127fd (patch) | |
| tree | 2152731d29341879972670a2f36b34e0fca48e09 | |
| parent | 04bc287271354d3a1770ae7a9f8f1de9341b9253 (diff) | |
| download | yosys-5f8f0e13833ef052adb4d2d3deb8e965734127fd.tar.gz yosys-5f8f0e13833ef052adb4d2d3deb8e965734127fd.tar.bz2 yosys-5f8f0e13833ef052adb4d2d3deb8e965734127fd.zip | |
Tidy up
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index e611bfb3b..afbd6ef81 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -390,11 +390,6 @@ endcode subpattern in_dffe arg dffQ clock dffenpol_ -code - dff = nullptr; - dffmux = nullptr; -endcode - match ff select ff->type.in($dff) // DSP48E1 does not support clock inversion @@ -428,8 +423,10 @@ code dffQ if (!(nusers(dffQ) >= 3 && nusers(dffD) == 2)) dffQ = SigSpec(); } - else + else { + dff = nullptr; dffQ = SigSpec(); + } endcode match ffmux @@ -454,4 +451,6 @@ code dffenpol = dffenpol_; dffD = port(ffmux, dffenpol ? \B : \A); } + else + dffmux = nullptr; endcode |