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| author | whitequark <whitequark@whitequark.org> | 2020-04-09 03:58:07 +0000 | 
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-09 03:58:07 +0000 | 
| commit | 570f43ec911837a4d0a0b888099b4adebdc3ff8c (patch) | |
| tree | fea53609960cbc9636b4dfe2016becbccee5b86b | |
| parent | 5f649fc19d5cef76a634572ad0a493f1d2fd6306 (diff) | |
| parent | 64a5936bd7d310727aa9024ff07f9a502488398b (diff) | |
| download | yosys-570f43ec911837a4d0a0b888099b4adebdc3ff8c.tar.gz yosys-570f43ec911837a4d0a0b888099b4adebdc3ff8c.tar.bz2 yosys-570f43ec911837a4d0a0b888099b4adebdc3ff8c.zip  | |
Merge pull request #1886 from boqwxp/cleanup_connect
Clean up `passes/cmds/connect.cc`.
| -rw-r--r-- | passes/cmds/connect.cc | 26 | 
1 files changed, 12 insertions, 14 deletions
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index f93bada27..0b0868dfb 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -32,9 +32,9 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &  	RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); -	for (auto &it : module->cells_) -	for (auto &port : it.second->connections_) -		if (ct.cell_output(it.second->type, port.first)) +	for (auto cell : module->cells()) +	for (auto &port : cell->connections_) +		if (ct.cell_output(cell->type, port.first))  			sigmap(port.second).replace(sig, dummy_wire, &port.second);  	for (auto &conn : module->connections_) @@ -77,15 +77,13 @@ struct ConnectPass : public Pass {  	}  	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE  	{ -		RTLIL::Module *module = NULL; -		for (auto &it : design->modules_) { -			if (!design->selected(it.second)) -				continue; -			if (module != NULL) -				log_cmd_error("Multiple modules selected: %s, %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.first)); -			module = it.second; +		RTLIL::Module *module = nullptr; +		for (auto mod : design->selected_modules()) { +			if (module != nullptr) +				log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name)); +			module = mod;  		} -		if (module == NULL) +		if (module == nullptr)  			log_cmd_error("No modules selected.\n");  		if (!module->processes.empty())  			log_cmd_error("Found processes in selected module.\n"); @@ -130,7 +128,7 @@ struct ConnectPass : public Pass {  				std::vector<RTLIL::SigBit> lhs = it.first.to_sigbit_vector();  				std::vector<RTLIL::SigBit> rhs = it.first.to_sigbit_vector();  				for (size_t i = 0; i < lhs.size(); i++) -					if (rhs[i].wire != NULL) +					if (rhs[i].wire != nullptr)  						sigmap.add(lhs[i], rhs[i]);  			} @@ -172,14 +170,14 @@ struct ConnectPass : public Pass {  			if (flag_nounset)  				log_cmd_error("Can't use -port together with -nounset.\n"); -			if (module->cells_.count(RTLIL::escape_id(port_cell)) == 0) +			if (module->cell(RTLIL::escape_id(port_cell)) == nullptr)  				log_cmd_error("Can't find cell %s.\n", port_cell.c_str());  			RTLIL::SigSpec sig;  			if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))  				log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str()); -			module->cells_.at(RTLIL::escape_id(port_cell))->setPort(RTLIL::escape_id(port_port), sigmap(sig)); +			module->cell(RTLIL::escape_id(port_cell))->setPort(RTLIL::escape_id(port_port), sigmap(sig));  		}  		else  			log_cmd_error("Expected -set, -unset, or -port.\n");  | 
