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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-30 07:48:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-30 07:48:47 -0700 |
| commit | 5017ff4a978ae92a3a00d120bed29de9425108aa (patch) | |
| tree | 7954f8ba19405283defa5e9c2f26a733b9b1f97d | |
| parent | 97bfe65d3a14586eaa99da2c5d007094e4834a50 (diff) | |
| download | yosys-5017ff4a978ae92a3a00d120bed29de9425108aa.tar.gz yosys-5017ff4a978ae92a3a00d120bed29de9425108aa.tar.bz2 yosys-5017ff4a978ae92a3a00d120bed29de9425108aa.zip | |
verific: ignore anonymous enums
| -rw-r--r-- | frontends/verific/verific.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index b818d01f7..fe4bda68e 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -172,7 +172,10 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att return; if (nl->IsFromVhdl() && strcmp(type_range->GetTypeName(), "STD_LOGIC") == 0) return; - attributes.emplace(ID::wiretype, RTLIL::escape_id(type_range->GetTypeName())); + auto type_name = type_range->GetTypeName(); + if (!type_name) + return; + attributes.emplace(ID::wiretype, RTLIL::escape_id(type_name)); MapIter mi; const char *k, *v; |