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| author | Clifford Wolf <clifford@clifford.at> | 2015-12-07 03:32:20 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-12-07 03:32:20 +0100 |
| commit | 4d0a6dac7b865a38b587cda3e1c13b16ee284deb (patch) | |
| tree | 53335c406dea1d9ea3dfbc9fa8b9f6c51107ea71 | |
| parent | 1ea6db3db82e933099ca285f5d483cb7fdb70f02 (diff) | |
| parent | 9f5b6e4cbc4da0b3ae6429b03097532de3bf4c60 (diff) | |
| download | yosys-4d0a6dac7b865a38b587cda3e1c13b16ee284deb.tar.gz yosys-4d0a6dac7b865a38b587cda3e1c13b16ee284deb.tar.bz2 yosys-4d0a6dac7b865a38b587cda3e1c13b16ee284deb.zip | |
Merge pull request #108 from cseed/master
Added LO to ICESTORM_LC for LUT cascade route.
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 4d792c856..f23218c00 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -661,7 +661,7 @@ endmodule module ICESTORM_LC ( input I0, I1, I2, I3, CIN, CLK, CEN, SR, - output O, COUT + output LO, O, COUT ); parameter [15:0] LUT_INIT = 0; @@ -678,6 +678,8 @@ module ICESTORM_LC ( wire [1:0] lut_s1 = I1 ? lut_s2[ 3:2] : lut_s2[1:0]; wire lut_o = I0 ? lut_s1[ 1] : lut_s1[ 0]; + assign LO = lut_o; + wire polarized_clk; assign polarized_clk = CLK ^ NEG_CLK; |