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author | Eddie Hung <eddie@fpgeh.com> | 2019-05-24 18:32:02 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-24 18:32:02 -0700 |
commit | 4bd9465ed3eb3ba2c0f45830b3337eaace4ec562 (patch) | |
tree | 099a7aac4bff7810905691673d1c842b5736d648 | |
parent | 822d0b7789fdfe94bfe11b96546af8430e5f3299 (diff) | |
download | yosys-4bd9465ed3eb3ba2c0f45830b3337eaace4ec562.tar.gz yosys-4bd9465ed3eb3ba2c0f45830b3337eaace4ec562.tar.bz2 yosys-4bd9465ed3eb3ba2c0f45830b3337eaace4ec562.zip |
Call proc
-rw-r--r-- | tests/various/opt_rmdff.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/various/opt_rmdff.ys b/tests/various/opt_rmdff.ys index fffffb4b5..89cd3f0c8 100644 --- a/tests/various/opt_rmdff.ys +++ b/tests/various/opt_rmdff.ys @@ -2,12 +2,12 @@ read_verilog -icells opt_rmdff.v prep design -stash gold read_verilog -icells opt_rmdff.v +proc opt_rmdff select -assert-count 0 c:remove* select -assert-min 7 c:keep* -prep design -stash gate design -import gold -as gold |