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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-28 08:44:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-28 08:44:59 -0700 |
| commit | 4a76b425cc0588ef5a8e46c06eecbfab869a35d9 (patch) | |
| tree | 8f0c57f5b81eab6d4fee60d0d917cb57f981af32 | |
| parent | 89bd6b85045b371c1088004d8e4af0dd78a3981d (diff) | |
| download | yosys-4a76b425cc0588ef5a8e46c06eecbfab869a35d9.tar.gz yosys-4a76b425cc0588ef5a8e46c06eecbfab869a35d9.tar.bz2 yosys-4a76b425cc0588ef5a8e46c06eecbfab869a35d9.zip | |
Misspell
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 1b45085be..328f0e3c3 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -567,7 +567,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // Attempt another wideports_split here because there // exists the possibility that different bits of a port - // could be an input and output, therefore parse_xiager() + // could be an input and output, therefore parse_xaiger() // could not combine it into a wideport auto r = wideports_split(w->name.str()); wire = module->wire(r.first); |