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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:31:22 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:31:22 -0700 |
| commit | 494610911ae2a5b2b73d0f5e030f237df56d3fb5 (patch) | |
| tree | 105d0b64e41eea8ffc33f8c4725f549f3ca96587 | |
| parent | c421d48d6d5519b24b4596d695c3cf7c43b468f4 (diff) | |
| download | yosys-494610911ae2a5b2b73d0f5e030f237df56d3fb5.tar.gz yosys-494610911ae2a5b2b73d0f5e030f237df56d3fb5.tar.bz2 yosys-494610911ae2a5b2b73d0f5e030f237df56d3fb5.zip | |
Fix different abc9 test
| -rw-r--r-- | backends/aiger/xaiger.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index f0a9ccdb9..55a95d835 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -406,13 +406,14 @@ struct XAigerWriter } for (auto bit : input_bits) { + if (!output_bits.count(bit)) + continue; RTLIL::Wire *wire = bit.wire; // If encountering an inout port, or a keep-ed wire, then create a new wire // with $inout.out suffix, make it a PO driven by the existing inout, and // inherit existing inout's drivers - if ((wire->port_input && wire->port_output && output_bits.count(bit) && !undriven_bits.count(bit)) + if ((wire->port_input && wire->port_output && !undriven_bits.count(bit)) || wire->attributes.count("\\keep")) { - log_assert(output_bits.count(bit)); RTLIL::IdString wire_name = wire->name.str() + "$inout.out"; RTLIL::Wire *new_wire = module->wire(wire_name); if (!new_wire) |