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| author | Clifford Wolf <clifford@clifford.at> | 2018-01-07 16:35:22 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-01-07 16:35:22 +0100 |
| commit | 446ccf1f05b2b36db9161bf4ab050778a1cbaee6 (patch) | |
| tree | 70734dddfc169601fd21e16b472f8aad20a4b2bd | |
| parent | b55798957695d965384019d5a220438c930e73ec (diff) | |
| download | yosys-446ccf1f05b2b36db9161bf4ab050778a1cbaee6.tar.gz yosys-446ccf1f05b2b36db9161bf4ab050778a1cbaee6.tar.bz2 yosys-446ccf1f05b2b36db9161bf4ab050778a1cbaee6.zip | |
Bugfix in hierarchy blackbox module port width handling
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index c680dbbd8..898763c64 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -621,8 +621,9 @@ struct HierarchyPass : public Pass { } std::set<Module*> blackbox_derivatives; + std::vector<Module*> design_modules = design->modules(); - for (auto module : design->modules()) + for (auto module : design_modules) for (auto cell : module->cells()) { Module *m = design->module(cell->type); |