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authorEddie Hung <eddie@fpgeh.com>2019-04-19 08:44:53 -0700
committerEddie Hung <eddie@fpgeh.com>2019-04-19 08:44:53 -0700
commit35f44f3ae8618b5e5da068c3df3d35b2fdc3d1aa (patch)
tree01669c0c0f8e7b71307c16fe4125767a7b6d68a9
parent3544a7cd7b6b2595d25c56c5b1c3fbf6c9cccf7e (diff)
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Do not assume inst_module is always present
-rw-r--r--backends/aiger/xaiger.cc21
1 files changed, 9 insertions, 12 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 71aaebfd9..31b74f9aa 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -193,12 +193,13 @@ struct XAigerWriter
continue;
}
- log_assert(inst_module);
- RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
- log_assert(inst_module_port);
+ if (inst_module) {
+ RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
+ log_assert(inst_module_port);
- if (inst_module_port->attributes.count("\\abc_flop_q"))
- continue;
+ if (inst_module_port->attributes.count("\\abc_flop_q"))
+ continue;
+ }
}
if (cell->input(conn.first)) {
@@ -254,7 +255,6 @@ struct XAigerWriter
// continue;
//}
- log_assert(inst_module);
if (inst_flop) {
SigBit d, q;
for (const auto &c : cell->connections()) {
@@ -279,7 +279,7 @@ struct XAigerWriter
ff_bits.emplace_back(d, q);
undriven_bits.erase(q);
}
- else if (!inst_module->attributes.count("\\abc_box_id")) {
+ else if (inst_module && !inst_module->attributes.count("\\abc_box_id")) {
for (const auto &c : cell->connections()) {
if (c.second.is_fully_const()) continue;
for (auto b : c.second.bits()) {
@@ -386,15 +386,12 @@ struct XAigerWriter
}
// Do some CI/CO post-processing:
- // Erase all POs and COs that are undriven
- for (auto bit : undriven_bits) {
- //co_bits.erase(bit);
+ // Erase all POs that are undriven
+ for (auto bit : undriven_bits)
output_bits.erase(bit);
- }
// CIs cannot be undriven
for (const auto &c : ci_bits)
undriven_bits.erase(c.first);
-
for (auto bit : unused_bits)
undriven_bits.erase(bit);