diff options
| author | Clifford Wolf <clifford@clifford.at> | 2019-03-07 09:08:26 -0800 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-03-07 09:08:26 -0800 |
| commit | 350dfd3745ec2efa92a601d3bab7712fd9bec07c (patch) | |
| tree | 8fb2f08e4f7a88796d3e7647a4eeaaced06197f7 | |
| parent | 8b0719d1e328751a50c0c07ec1fc65884fd119fc (diff) | |
| download | yosys-350dfd3745ec2efa92a601d3bab7712fd9bec07c.tar.gz yosys-350dfd3745ec2efa92a601d3bab7712fd9bec07c.tar.bz2 yosys-350dfd3745ec2efa92a601d3bab7712fd9bec07c.zip | |
Add link to SF2 / igloo2 macro library guide
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | techlibs/sf2/cells_sim.v | 45 |
1 files changed, 24 insertions, 21 deletions
diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v index f3f7695cf..c62748b11 100644 --- a/techlibs/sf2/cells_sim.v +++ b/techlibs/sf2/cells_sim.v @@ -1,3 +1,27 @@ +// https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf + +module ADD2 ( + + input A, B, + output Y +); + assign Y = A & B; +endmodule + +module ADD3 ( + input A, B, C, + output Y +); + assign Y = A & B & C; +endmodule + +module ADD4 ( + input A, B, C, D, + output Y +); + assign Y = A & B & C & D; +endmodule + module CFG1 ( output Y, input A @@ -36,27 +60,6 @@ module CFG4 ( assign Y = INIT >> {D, C, B, A}; endmodule -module ADD2 ( - input A, B, - output Y -); - assign Y = A & B; -endmodule - -module ADD3 ( - input A, B, C, - output Y -); - assign Y = A & B & C; -endmodule - -module ADD4 ( - input A, B, C, D, - output Y -); - assign Y = A & B & C & D; -endmodule - module BUFF ( input A, output Y |