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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 09:05:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 09:05:02 -0700 |
| commit | 2cbcd6224c0293a3abdf00f51c515fc556d9d3e1 (patch) | |
| tree | bf9b2cc5fe48eb26391124aee2abbe414404ec9f | |
| parent | 882a83c383e277e51083019227a88c38bc6b1c68 (diff) | |
| download | yosys-2cbcd6224c0293a3abdf00f51c515fc556d9d3e1.tar.gz yosys-2cbcd6224c0293a3abdf00f51c515fc556d9d3e1.tar.bz2 yosys-2cbcd6224c0293a3abdf00f51c515fc556d9d3e1.zip | |
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
This reverts commit a138381ac3f2c820d187f08531ffd823d6cbcfd5, reversing
changes made to b77c5da76919f7f99f171a0a2775896fbc8debc2.
| -rw-r--r-- | passes/techmap/shregmap.cc | 9 | ||||
| -rw-r--r-- | tests/various/shregmap.v | 22 | ||||
| -rw-r--r-- | tests/various/shregmap.ys | 31 |
3 files changed, 3 insertions, 59 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 46f6a79fb..21dfe9619 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -293,13 +293,10 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { - auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); - if (!r.second) { + if (sigbit_chain_next.count(d_bit)) { sigbit_with_non_chain_users.insert(d_bit); - Wire *wire = module->addWire(NEW_ID); - module->connect(wire, d_bit); - sigbit_chain_next.insert(std::make_pair(wire, cell)); - } + } else + sigbit_chain_next[d_bit] = cell; sigbit_chain_prev[q_bit] = cell; continue; diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v deleted file mode 100644 index 56e05c2c0..000000000 --- a/tests/various/shregmap.v +++ /dev/null @@ -1,22 +0,0 @@ -module shregmap_test(input i, clk, output [1:0] q); -reg head = 1'b0; -reg [3:0] shift1 = 4'b0000; -reg [3:0] shift2 = 4'b0000; - -always @(posedge clk) begin - head <= i; - shift1 <= {shift1[2:0], head}; - shift2 <= {shift2[2:0], head}; -end - -assign q = {shift2[3], shift1[3]}; -endmodule - -module $__SHREG_DFF_P_(input C, D, output Q); -parameter DEPTH = 1; -parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; -reg [DEPTH-1:0] r = INIT; -always @(posedge C) - r <= { r[DEPTH-2:0], D }; -assign Q = r[DEPTH-1]; -endmodule diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys deleted file mode 100644 index ca7f47015..000000000 --- a/tests/various/shregmap.ys +++ /dev/null @@ -1,31 +0,0 @@ -read_verilog shregmap.v -design -copy-to model $__SHREG_DFF_P_ -hierarchy -top shregmap_test -prep -design -save gold - -techmap -shregmap -init - -opt - -stat -# show -width -select -assert-count 1 t:$_DFF_P_ -select -assert-count 2 t:$__SHREG_DFF_P_ - -design -stash gate - -design -import gold -as gold -design -import gate -as gate -design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_ -prep - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports -seq 5 miter - -design -load gold -stat - -design -load gate -stat |