diff options
| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-14 15:39:11 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-14 15:39:11 +0100 |
| commit | 27c5bafc956b0dac22ef009645c15fe2eef326b7 (patch) | |
| tree | d605720cee019960b8d1cbcb8270359f163adf71 | |
| parent | a502570c250ba36900f4f9e5db1c65aa1eeb8bb6 (diff) | |
| download | yosys-27c5bafc956b0dac22ef009645c15fe2eef326b7.tar.gz yosys-27c5bafc956b0dac22ef009645c15fe2eef326b7.tar.bz2 yosys-27c5bafc956b0dac22ef009645c15fe2eef326b7.zip | |
Proper example code
| -rw-r--r-- | tests/sat/grom_cpu.v | 2 | ||||
| -rw-r--r-- | tests/sat/ram_memory.v | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/tests/sat/grom_cpu.v b/tests/sat/grom_cpu.v index f9fef043b..914c0f56c 100644 --- a/tests/sat/grom_cpu.v +++ b/tests/sat/grom_cpu.v @@ -185,7 +185,7 @@ module grom_cpu( `ifdef DISASSEMBLY $display("INC R%d",IR[1:0]); `endif - alu_op <= 4'b0001; // ALU_OP_ADD + alu_op <= 4'b0000; // ALU_OP_ADD end 2'b01 : begin `ifdef DISASSEMBLY diff --git a/tests/sat/ram_memory.v b/tests/sat/ram_memory.v index 053ef206c..0d91514b2 100644 --- a/tests/sat/ram_memory.v +++ b/tests/sat/ram_memory.v @@ -27,6 +27,8 @@ module ram_memory( store[256] <= 8'b11010001; // OUT [0],R1 store[257] <= 8'b00000000; // store[258] <= 8'b01111110; // RET + + store[512] <= 8'b00000000; end always @(posedge clk) |