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author | Clifford Wolf <clifford@clifford.at> | 2014-06-14 16:42:30 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-06-14 16:45:16 +0200 |
commit | 1a487303a081849bd7561772641f90126dcce24e (patch) | |
tree | 8dee6bb844b53f78061fb48896995ea38c14e6ca | |
parent | 22a998903b14b93180b98fe71129160e27793e38 (diff) | |
download | yosys-1a487303a081849bd7561772641f90126dcce24e.tar.gz yosys-1a487303a081849bd7561772641f90126dcce24e.tar.bz2 yosys-1a487303a081849bd7561772641f90126dcce24e.zip |
Progress in presentation
-rw-r--r-- | manual/PRESENTATION_ExOth.tex | 66 | ||||
-rw-r--r-- | manual/PRESENTATION_ExOth/.gitignore | 1 | ||||
-rw-r--r-- | manual/PRESENTATION_ExOth/Makefile | 8 | ||||
-rw-r--r-- | manual/PRESENTATION_ExOth/scrambler.v | 14 | ||||
-rw-r--r-- | manual/PRESENTATION_ExOth/scrambler.ys | 23 |
5 files changed, 109 insertions, 3 deletions
diff --git a/manual/PRESENTATION_ExOth.tex b/manual/PRESENTATION_ExOth.tex index 13ec3d193..64c4af721 100644 --- a/manual/PRESENTATION_ExOth.tex +++ b/manual/PRESENTATION_ExOth.tex @@ -23,10 +23,70 @@ This section contains 3 subsections: \subsectionpagesuffix \end{frame} -\subsubsection{TBD} +\begin{frame}{\subsecname} +Yosys can also be used to investigate designs (or netlists created +from other tools). -\begin{frame}{\subsubsecname} -TBD +\begin{itemize} +\item +The selection mechanism (see slides ``Using Selections''), especially pattern such +as {\tt \%ci} and {\tt \%co}, can be used to figure out how parts of the design +are connected. + +\item +Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used +to transform the design into an equivialent design that is easier to analyse. + +\item +Commands such as {\tt eval} and {\tt sat} can be used to investigate the +behavior of the circuit. +\end{itemize} +\end{frame} + +\begin{frame}[t, fragile]{Example: Reorganizing a module} +\begin{columns} +\column[t]{4cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExOth/scrambler.v} +\column[t]{7cm} +\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single] +read_verilog scrambler.v + +hierarchy; proc;; + +cd scrambler +submod -name xorshift32 xs %c %ci %D \ + %c %ci:+[D] %D %ci*:-$dff \ + xs %co %ci %d +\end{lstlisting} +\end{columns} + +\hfil\includegraphics[width=11cm,trim=0 0cm 0 1.5cm]{PRESENTATION_ExOth/scrambler_p01.pdf} + +\hfil\includegraphics[width=11cm,trim=0 0cm 0 2cm]{PRESENTATION_ExOth/scrambler_p02.pdf} +\end{frame} + +\begin{frame}[t, fragile]{Example: Analysis of circuit behavior} +\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +> read_verilog scrambler.v +> hierarchy; proc;; cd scrambler +> submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d + +> cd xorshift32 +> rename n2 in +> rename n1 out + +> eval -set in 1 -show out +Eval result: \out = 270369. + +> eval -set in 270369 -show out +Eval result: \out = 67634689. + +> sat -set out 632435482 +Signal Name Dec Hex Bin +-------------------- ---------- ---------- ------------------------------------- +\in 745495504 2c6f5bd0 00101100011011110101101111010000 +\out 632435482 25b2331a 00100101101100100011001100011010 +\end{lstlisting} \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% diff --git a/manual/PRESENTATION_ExOth/.gitignore b/manual/PRESENTATION_ExOth/.gitignore new file mode 100644 index 000000000..cf658897d --- /dev/null +++ b/manual/PRESENTATION_ExOth/.gitignore @@ -0,0 +1 @@ +*.dot diff --git a/manual/PRESENTATION_ExOth/Makefile b/manual/PRESENTATION_ExOth/Makefile new file mode 100644 index 000000000..a12beadad --- /dev/null +++ b/manual/PRESENTATION_ExOth/Makefile @@ -0,0 +1,8 @@ + +all: scrambler_p01.pdf scrambler_p02.pdf + +scrambler_p01.pdf: scrambler.ys scrambler.v + ../../yosys scrambler.ys + +scrambler_p02.pdf: scrambler_p01.pdf + diff --git a/manual/PRESENTATION_ExOth/scrambler.v b/manual/PRESENTATION_ExOth/scrambler.v new file mode 100644 index 000000000..d4c1fa2bb --- /dev/null +++ b/manual/PRESENTATION_ExOth/scrambler.v @@ -0,0 +1,14 @@ +module scrambler( + input clk, rst, in_bit, + output reg out_bit +); + reg [31:0] xs; + always @(posedge clk) begin + if (rst) + xs = 1; + xs = xs ^ (xs << 13); + xs = xs ^ (xs >> 17); + xs = xs ^ (xs << 5); + out_bit <= in_bit ^ xs[0]; + end +endmodule diff --git a/manual/PRESENTATION_ExOth/scrambler.ys b/manual/PRESENTATION_ExOth/scrambler.ys new file mode 100644 index 000000000..2ef14c56e --- /dev/null +++ b/manual/PRESENTATION_ExOth/scrambler.ys @@ -0,0 +1,23 @@ + +read_verilog scrambler.v + +hierarchy; proc;; + +cd scrambler +submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d +cd .. + +show -prefix scrambler_p01 -format pdf -notitle scrambler +show -prefix scrambler_p02 -format pdf -notitle xorshift32 + +echo on + +cd xorshift32 +rename n2 in +rename n1 out + +eval -set in 1 -show out +eval -set in 270369 -show out + +sat -set out 632435482 + |