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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 16:40:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 16:40:30 -0700 |
| commit | 1826370b3ab1485f966a796b95860779ae1dbd69 (patch) | |
| tree | 8adfc43fac1d0a4f743a9a71b915f22a80f1b309 | |
| parent | 1dce798dc5050745490600c09c873d821548f4f7 (diff) | |
| download | yosys-1826370b3ab1485f966a796b95860779ae1dbd69.tar.gz yosys-1826370b3ab1485f966a796b95860779ae1dbd69.tar.bz2 yosys-1826370b3ab1485f966a796b95860779ae1dbd69.zip | |
xaiger: promote abc9_keep wires
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 6b910eecd..4a8f54c4d 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -156,7 +156,7 @@ struct XAigerWriter // promote keep wires for (auto wire : module->wires()) - if (wire->get_bool_attribute(ID::keep)) + if (wire->get_bool_attribute(ID::keep) || wire->get_bool_attribute(ID::abc9_keep)) sigmap.add(wire); for (auto wire : module->wires()) { |