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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-27 23:07:21 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-27 23:07:21 -0700 |
| commit | 134e093e4e86080e1e4066f32128d268a36aeee5 (patch) | |
| tree | 809150f2bc7fe48371714fd5c752f3f25bc045f5 | |
| parent | 0d2923cccd00ed14537f3239b0059a76673798a4 (diff) | |
| download | yosys-134e093e4e86080e1e4066f32128d268a36aeee5.tar.gz yosys-134e093e4e86080e1e4066f32128d268a36aeee5.tar.bz2 yosys-134e093e4e86080e1e4066f32128d268a36aeee5.zip | |
Added GP_PGA cell
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 1152ffe63..b7dbe81a2 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -153,6 +153,17 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT); endmodule +module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT); + + parameter GAIN = 1; + parameter INPUT_MODE = "SINGLE"; + + initial VOUT = 0; + + //cannot simulate mixed signal IP + +endmodule + module GP_POR(output reg RST_DONE); parameter POR_TIME = 500; |