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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-19 20:35:31 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-19 20:35:31 +0100 |
| commit | 0dfdbd991afcbcc38110d22d489969ae33fb1f68 (patch) | |
| tree | e30b5665c7ed0f0b43c5f7bcdb3b96b960165650 | |
| parent | 63285b300ca8a3057345f6b28ee20ff709ede24d (diff) | |
| download | yosys-0dfdbd991afcbcc38110d22d489969ae33fb1f68.tar.gz yosys-0dfdbd991afcbcc38110d22d489969ae33fb1f68.tar.bz2 yosys-0dfdbd991afcbcc38110d22d489969ae33fb1f68.zip | |
Fixed parsing of module arguments when one type is used for many args
| -rw-r--r-- | frontends/verilog/parser.y | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index 17f14d541..1dcc0d6cc 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -248,9 +248,16 @@ optional_comma: module_arg: TOK_ID range { - if (port_stubs.count(*$1) != 0) - frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str()); - port_stubs[*$1] = ++port_counter; + if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) { + AstNode *node = ast_stack.back()->children.back()->clone(); + node->str = *$1; + node->port_id = ++port_counter; + ast_stack.back()->children.push_back(node); + } else { + if (port_stubs.count(*$1) != 0) + frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str()); + port_stubs[*$1] = ++port_counter; + } if ($2 != NULL) delete $2; delete $1; |