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author | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 17:50:30 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 17:50:30 -0700 |
commit | 988d47af8533a0c7728095862dbc6a7311c1f8b7 (patch) | |
tree | 1574fa5d122982cdf43ae120630eb5c82bda35f3 /.travis.yml | |
parent | 592baebd22ab1c80512b6f91926d90b33393285e (diff) | |
download | yosys-988d47af8533a0c7728095862dbc6a7311c1f8b7.tar.gz yosys-988d47af8533a0c7728095862dbc6a7311c1f8b7.tar.bz2 yosys-988d47af8533a0c7728095862dbc6a7311c1f8b7.zip |
tests: read +/xilinx/cell_sim.v before xilinx_dsp test
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