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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-18 15:31:27 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-18 15:31:27 +0200 |
| commit | 927f0caa9d70ccf3634b29d8558c78febcc9081c (patch) | |
| tree | c34e46ade9cd99dc38eff34b2b71574464b4b64c /.github | |
| parent | 56c00e871fbb73649d3b6f7ccee31c90942a020c (diff) | |
| parent | 4ff44d85a5cb63c7b3f67c2f2398e62db7f199eb (diff) | |
| download | yosys-927f0caa9d70ccf3634b29d8558c78febcc9081c.tar.gz yosys-927f0caa9d70ccf3634b29d8558c78febcc9081c.tar.bz2 yosys-927f0caa9d70ccf3634b29d8558c78febcc9081c.zip | |
Merge pull request #1203 from whitequark/write_verilog-zero-width-values
write_verilog: dump zero width constants correctly
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