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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 17:34:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 17:34:40 -0700 |
| commit | 15188033da68c89c409af0839f22e6acc573abb7 (patch) | |
| tree | 26cd2808fbcedddf0d86d071edcb17de432c6a7c /.github | |
| parent | 6d76ae4c65d3a7b403888219900a3c0f85ee737d (diff) | |
| download | yosys-15188033da68c89c409af0839f22e6acc573abb7.tar.gz yosys-15188033da68c89c409af0839f22e6acc573abb7.tar.bz2 yosys-15188033da68c89c409af0839f22e6acc573abb7.zip | |
Add variable length support to xilinx_srl
Diffstat (limited to '.github')
0 files changed, 0 insertions, 0 deletions