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| author | Claire Xenia Wolf <claire@symbioticeda.com> | 2020-10-01 18:26:53 +0200 |
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| committer | Claire Xenia Wolf <claire@symbioticeda.com> | 2020-10-01 18:27:16 +0200 |
| commit | 46f0932c4c61aca3ab5332f99a4a60d110b52191 (patch) | |
| tree | c33b214a81a2967dd550b93339ba1b9cf0596a07 /.editorconfig | |
| parent | 7e2fc2eaeb70179c8da3e5dc8be800f486d5b912 (diff) | |
| download | yosys-46f0932c4c61aca3ab5332f99a4a60d110b52191.tar.gz yosys-46f0932c4c61aca3ab5332f99a4a60d110b52191.tar.bz2 yosys-46f0932c4c61aca3ab5332f99a4a60d110b52191.zip | |
Ignore empty parameters in Verilog module instantiations
Fixes #2394
Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
Diffstat (limited to '.editorconfig')
0 files changed, 0 insertions, 0 deletions