/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "kernel/register.h" #include "kernel/celltypes.h" #include "kernel/rtlil.h" #include "kernel/log.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct PrepPass : public ScriptPass { PrepPass() : ScriptPass("prep", "generic synthesis script") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" prep [options]\n"); log("\n"); log("This command runs a conservative RTL synthesis. A typical application for this\n"); log("is the preparation stage of a verification flow. This command does not operate\n"); log("on partly selected designs.\n"); log("\n"); log(" -top \n"); log(" use the specified module as top module (default='top')\n"); log("\n"); log(" -auto-top\n"); log(" automatically determine the top of the design hierarchy\n"); log("\n"); log(" -flatten\n"); log(" flatten the design before synthesis. this will pass '-auto-top' to\n"); log(" 'hierarchy' if no top module is specified.\n"); log("\n"); log(" -ifx\n"); log(" passed to 'proc'. uses verilog simulation behavior for verilog if/case\n"); log(" undef handling. this also prevents 'wreduce' from being run.\n"); log("\n"); log(" -memx\n"); log(" simulate verilog simulation behavior for out-of-bounds memory accesses\n"); log(" using the 'memory_memx' pass.\n"); log("\n"); log(" -nomem\n"); log(" do not run any of the memory_* passes\n"); log("\n"); log(" -rdff\n"); log(" call 'memory_dff'. This enables merging of FFs into\n"); log(" memory read ports.\n"); log("\n"); log(" -nokeepdc\n"); log(" do not call opt_* with -keepdc\n"); log("\n"); log(" -run [:]\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); log(" synonymous to the end of the command list.\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script()

ctx.writeSVG(ctx.top_module + "_routed.svg", "scale=500 hide_inactive")