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path: root/fpga_interchange/examples/tests/wire/arty100t.xdc
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module test(input      CLK, ADDR,
            input      [7:0] DIN,
	    output reg [7:0] DOUT);
    reg [7:0] mem [0:1];
    always @(posedge CLK) begin
        mem[ADDR] <= DIN;
	DOUT <= mem[ADDR];
    end
endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-02 11:30:45 +0000