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path:
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/
fpga_interchange
/
examples
/
const_wire
/
wire.v
blob: 7905c92e348c4f5d1fa59aff39b796d6a54f703b (
plain
)
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module
top
(
output
o
,
output
o2
);
assign
o
=
1
'b0
;
assign
o2
=
1
'b1
;
endmodule