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import pytest
import re

from pybind11_tests import factory_constructors as m
from pybind11_tests.factory_constructors import tag
from pybind11_tests import ConstructorStats


def test_init_factory_basic():
    """Tests py::init_factory() wrapper around various ways of returning the object"""

    cstats = [ConstructorStats.get(c) for c in [m.TestFactory1, m.TestFactory2, m.TestFactory3]]
    cstats[0].alive()  # force gc
    n_inst = ConstructorStats.detail_reg_inst()

    x1 = m.TestFactory1(tag.unique_ptr, 3)
    assert x1.value == "3"
    y1 = m.TestFactory1(tag.pointer)
    assert y1.value == "(empty)"
    z1 = m.TestFactory1("hi!")
    assert z1.value == "hi!"

    assert ConstructorStats.detail_reg_inst() == n_inst + 3

    x2 = m.TestFactory2(tag.move)
    assert x2.value == "(empty2)"
    y2 = m.TestFactory2(tag.pointer, 7)
    assert y2.value == "7"
    z2 = m.TestFactory2(tag.unique_ptr, "hi again")
    assert z2.value == "hi again"

    assert ConstructorStats.detail_reg_inst() == n_inst + 6

    x3 = m.TestFactory3(tag.shared_ptr)
    assert x3.value == "(empty3)"
    y3 = m.TestFactory3(tag.pointer, 42)
    assert y3.value == "42"
    z3 = m.TestFactory3("bye")
    assert z3.value == "bye"

    with pytest.raises(TypeError) as excinfo:
        m.TestFactory3(tag.null_ptr)
    assert str(excinfo.value) == "pybind11::init(): factory function returned nullptr"

    assert [i.alive() for i in cstats] == [3, 3, 3]
    assert ConstructorStats.detail_reg_inst() == n_inst + 9

    del x1, y2, y3, z3
    assert [i.alive() for i in cstats] == [2, 2, 1]
    assert ConstructorStats.detail_reg_inst() == n_inst + 5
    del x2, x3, y1, z1, z2
    assert [i.alive() for i in cstats] == [0, 0, 0]
    assert ConstructorStats.detail_reg_inst() == n_inst

    assert [i.values() for i in cstats] == [
        ["3", "hi!"],
        ["7", "hi again"],
        ["42", "bye"]
    ]
    assert [i.default_constructions for i in cstats] == [1, 1, 1]


def test_init_factory_signature(msg):
    with pytest.raises(TypeError) as excinfo:
        m.TestFactory1("invalid", "constructor", "arguments")
    assert msg(excinfo.value) == """
        __init__(): incompatible constructor arguments. The following argument types are supported:
            1. m.factory_constructors.TestFactory1(arg0: m.factory_constructors.tag.unique_ptr_tag, arg1: int)
            2. m.factory_constructors.TestFactory1(arg0: str)
            3. m.factory_constructors.TestFactory1(arg0: m.factory_constructors.tag.pointer_tag)
            4. m.factory_constructors.TestFactory1(arg0: handle, arg1: int, arg2: handle)

        Invoked with: 'invalid', 'constructor', 'arguments'
    """  # noqa: E501 line too long

    assert msg(m.TestFactory1.__init__.__doc__) == """
        __init__(*args, **kwargs)
        Overloaded function.

        1. __init__(self: m.factory_constructors.TestFactory1, arg0: m.factory_constructors.tag.unique_ptr_tag, arg1: int) -> None

        2. __init__(self: m.factory_constructors.TestFactory1, arg0: str) -> None

        3. __init__(self: m.factory_constructors.TestFactory1, arg0: m.factory_constructors.tag.pointer_tag) -> None

        4. __init__(self: m.factory_constructors.TestFactory1, arg0: handle, arg1: int, arg2: handle) -> None
    """  # noqa: E501 line too long


def test_init_factory_casting():
    """Tests py::init_factory() wrapper with various upcasting and downcasting returns"""

    cstats = [ConstructorStats.get(c) for c in [m.TestFactory3, m.TestFactory4, m.TestFactory5]]
    cstats[0].alive()  # force gc
    n_inst = ConstructorStats.detail_reg_inst()

    # Construction from derived references:
    a = m.TestFactory3(tag.pointer, tag.TF4, 4)
    assert a.value == "4"
    b = m.TestFactory3(tag.shared_ptr, tag.TF4, 5)
    assert b.value == "5"
    c = m.TestFactory3(tag.pointer, tag.TF5, 6)
    assert c.value == "6"
    d = m.TestFactory3(tag.shared_ptr, tag.TF5, 7)
    assert d.value == "7"

    assert ConstructorStats.detail_reg_inst() == n_inst + 4

    # Shared a lambda with TF3:
    e = m.TestFactory4(tag.pointer, tag.TF4, 8)
    assert e.value == "8"

    assert ConstructorStats.detail_reg_inst() == n_inst + 5
    assert [i.alive() for i in cstats] == [5, 3, 2]

    del a
    assert [i.alive() for i in cstats] == [4, 2, 2]
    assert ConstructorStats.detail_reg_inst() == n_inst + 4

    del b, c, e
    assert [i.alive() for i in cstats] == [1, 0, 1]
    assert ConstructorStats.detail_reg_inst() == n_inst + 1

    del d
    assert [i.alive() for i in cstats] == [0, 0, 0]
    assert ConstructorStats.detail_reg_inst() == n_inst

    assert [i.values() for i in cstats] == [
        ["4", "5", "6", "7", "8"],
        ["4", "5", "8"],
        ["6", "7"]
    ]


def test_init_factory_alias():
    """Tests py::init_factory() wrapper with value conversions and alias types"""

    cstats = [m.TestFactory6.get_cstats(), m.TestFactory6.get_alias_cstats()]
    cstats[0].alive()  # force gc
    n_inst = ConstructorStats.detail_reg_inst()

    a = m.TestFactory6(tag.base, 1)
    assert a.get() == 1
    assert not a.has_alias()
    b = m.TestFactory6(tag.alias, "hi there")
    assert b.get() == 8
    assert b.has_alias()
    c = m.TestFactory6(tag.alias, 3)
    assert c.get() == 3
    assert c.has_alias()
    d = m.TestFactory6(tag.alias, tag.pointer, 4)
    assert d.get() == 4
    assert d.has_alias()
    e = m.TestFactory6(tag.base, tag.pointer, 5)
    assert e.get() == 5
    assert not e.has_alias()
    f = m.TestFactory6(tag.base, tag.alias, tag.pointer, 6)
    assert f.get() == 6
    assert f.has_alias()

    assert ConstructorStats.detail_reg_inst() == n_inst + 6
    assert [i.alive() for i in cstats] == [6, 4]

    del a, b, e
    assert [i.alive() for i in cstats] == [3, 3]
    assert ConstructorStats.detail_reg_inst() == n_inst + 3
    del f, c, d
    assert [i.alive() for i in cstats] == [0, 0]
    assert ConstructorStats.detail_reg_inst() == n_inst

    class MyTest(m.TestFactory6):
        def __init__(self, *args):
            m.TestFactory6.__init__(self, *args)

        def get(self):
            return -5 + m.TestFactory6.get(self)

    # Return Class by value, moved into new alias:
    z = MyTest(tag.base, 123)
    assert z.get() == 118
    assert z.has_alias()

    # Return alias by value, moved into new alias:
    y = MyTest(tag.alias, "why hello!")
    assert y.get() == 5
    assert y.has_alias()

    # Return Class by pointer, moved into new alias then original destroyed:
    x = MyTest(tag.base, tag.pointer, 47)
    assert x.get() == 42
    assert x.has_alias()

    assert ConstructorStats.detail_reg_inst() == n_inst + 3
    assert [i.alive() for i in cstats] == [3, 3]
    del x, y, z
    assert [i.alive() for i in cstats] == [0, 0]
    assert ConstructorStats.detail_reg_inst() == n_inst

    assert [i.values() for i in cstats] == [
        ["1", "8", "3", "4", "5", "6", "123", "10", "47"],
        ["hi there", "3", "4", "6", "move", "123", "why hello!", "move", "47"]
    ]


def test_init_factory_dual():
    """Tests init factory functions with dual main/alias factory functions"""
    from pybind11_tests.factory_constructors import TestFactory7

    cstats = [TestFactory7.get_cstats(), TestFactory7.get_alias_cstats()]
    cstats[0].alive()  # force gc
    n_inst = ConstructorStats.detail_reg_inst()

    class PythFactory7(TestFactory7):
        def get(self):
            return 100 + TestFactory7.get(self)

    a1 = TestFactory7(1)
    a2 = PythFactory7(2)
    assert a1.get() == 1
    assert a2.get() == 102
    assert not a1.has_alias()
    assert a2.has_alias()

    b1 = TestFactory7(tag.pointer, 3)
    b2 = PythFactory7(tag.pointer, 4)
    assert b1.get() == 3
    assert b2.get() == 104
    assert not b1.has_alias()
    assert b2.has_alias()

    c1 = TestFactory7(tag.mixed, 5)
    c2 = PythFactory7(tag.mixed, 6)
    assert c1.get() == 5
    assert c2.get() == 106
    assert not c1.has_alias()
    assert c2.has_alias()

    d1 = TestFactory7(tag.base, tag.pointer, 7)
    d2 = PythFactory7(tag.base, tag.pointer, 8)
    assert d1.get() == 7
    assert d2.get() == 108
    assert not d1.has_alias()
    assert d2.has_alias()

    # Both return an alias; the second multiplies the value by 10:
    e1 = TestFactory7(tag.alias, tag.pointer, 9)
    e2 = PythFactory7(tag.alias, tag.pointer, 10)
    assert e1.get() == 9
    assert e2.get() == 200
    assert e1.has_alias()
    assert e2.has_alias()

    f1 = TestFactory7(tag.shared_ptr, tag.base, 11)
    f2 = PythFactory7(tag.shared_ptr, tag.base, 12)
    assert f1.get() == 11
    assert f2.get() == 112
    assert not f1.has_alias()
    assert f2.has_alias()

    g1 = TestFactory7(tag.shared_ptr, tag.invalid_base, 13)
    assert g1.get() == 13
    assert not g1.has_alias()
    with pytest.raises(TypeError) as excinfo:
        PythFactory7(tag.shared_ptr, tag.invalid_base, 14)
    assert (str(excinfo.value) ==
            "pybind11::init(): construction failed: returned holder-wrapped instance is not an "
            "alias instance")

    assert [i.alive() for i in cstats] == [13, 7]
    assert ConstructorStats.detail_reg_inst() == n_inst + 13

    del a1, a2, b1, d1, e1, e2
    assert [i.alive() for i in cstats] == [7, 4]
    assert ConstructorStats.detail_reg_inst() == n_inst + 7
    del b2, c1, c2, d2, f1, f2, g1
    assert [i.alive() for i in cstats] == [0, 0]
    assert ConstructorStats.detail_reg_inst() == n_inst

    assert [i.values() for i in cstats] == [
        ["1", "2", "3", "4", "5", "6", "7", "8", "9", "100", "11", "12", "13", "14"],
        ["2", "4", "6", "8", "9", "100", "12"]
    ]


def test_no_placement_new(capture):
    """Prior to 2.2, `py::init<...>` relied on the type supporting placement
    new; this tests a class without placement new support."""
    with capture:
        a = m.NoPlacementNew(123)

    found = re.search(r'^operator new called, returning (\d+)\n$', str(capture))
    assert found
    assert a.i == 123
    with capture:
        del a
        pytest.gc_collect()
    assert capture == "operator delete called on " + found.group(1)

    with capture:
        b = m.NoPlacementNew()

    found = re.search(r'^operator new called, returning (\d+)\n$', str(capture))
    assert found
    assert b.i == 100
    with capture:
        del b
        pytest.gc_collect()
    assert capture == "operator delete called on " + found.group(1)


def test_multiple_inheritance():
    class MITest(m.TestFactory1, m.TestFactory2):
        def __init__(self):
            m.TestFactory1.__init__(self, tag.unique_ptr, 33)
            m.TestFactory2.__init__(self, tag.move)

    a = MITest()
    assert m.TestFactory1.value.fget(a) == "33"
    assert m.TestFactory2.value.fget(a) == "(empty2)"


def create_and_destroy(*args):
    a = m.NoisyAlloc(*args)
    print("---")
    del a
    pytest.gc_collect()


def strip_comments(s):
    return re.sub(r'\s+#.*', '', s)


def test_reallocations(capture, msg):
    """When the constructor is overloaded, previous overloads can require a preallocated value.
    This test makes sure that such preallocated values only happen when they might be necessary,
    and that they are deallocated properly"""

    pytest.gc_collect()

    with capture:
        create_and_destroy(1)
    assert msg(capture) == """
        noisy new
        noisy placement new
        NoisyAlloc(int 1)
        ---
        ~NoisyAlloc()
        noisy delete
    """
    with capture:
        create_and_destroy(1.5)
    assert msg(capture) == strip_comments("""
        noisy new               # allocation required to attempt first overload
        noisy delete            # have to dealloc before considering factory init overload
        noisy new               # pointer factory calling "new", part 1: allocation
        NoisyAlloc(double 1.5)  # ... part two, invoking constructor
        ---
        ~NoisyAlloc()  # Destructor
        noisy delete   # operator delete
    """)

    with capture:
        create_and_destroy(2, 3)
    assert msg(capture) == strip_comments("""
        noisy new          # pointer factory calling "new", allocation
        NoisyAlloc(int 2)  # constructor
        ---
        ~NoisyAlloc()  # Destructor
        noisy delete   # operator delete
    """)

    with capture:
        create_and_destroy(2.5, 3)
    assert msg(capture) == strip_comments("""
        NoisyAlloc(double 2.5)  # construction (local func variable: operator_new not called)
        noisy new               # return-by-value "new" part 1: allocation
        ~NoisyAlloc()           # moved-away local func variable destruction
        ---
        ~NoisyAlloc()  # Destructor
        noisy delete   # operator delete
    """)

    with capture:
        create_and_destroy(3.5, 4.5)
    assert msg(capture) == strip_comments("""
        noisy new               # preallocation needed before invoking placement-new overload
        noisy placement new     # Placement new
        NoisyAlloc(double 3.5)  # construction
        ---
        ~NoisyAlloc()  # Destructor
        noisy delete   # operator delete
    """)

    with capture:
        create_and_destroy(4, 0.5)
    assert msg(capture) == strip_comments("""
        noisy new          # preallocation needed before invoking placement-new overload
        noisy delete       # deallocation of preallocated storage
        noisy new          # Factory pointer allocation
        NoisyAlloc(int 4)  # factory pointer construction
        ---
        ~NoisyAlloc()  # Destructor
        noisy delete   # operator delete
    """)

    with capture:
        create_and_destroy(5, "hi")
    assert msg(capture) == strip_comments("""
        noisy new            # preallocation needed before invoking first placement new
        noisy delete         # delete before considering new-style constructor
        noisy new            # preallocation for second placement new
        noisy placement new  # Placement new in the second placement new overload
        NoisyAlloc(int 5)    # construction
        ---
        ~NoisyAlloc()  # Destructor
        noisy delete   # operator delete
    """)


@pytest.unsupported_on_py2
def test_invalid_self():
    """Tests invocation of the pybind-registered base class with an invalid `self` argument.  You
    can only actually do this on Python 3: Python 2 raises an exception itself if you try."""
    class NotPybindDerived(object):
        pass

    # Attempts to initialize with an invalid type passed as `self`:
    class BrokenTF1(m.TestFactory1):
        def __init__(self, bad):
            if bad == 1:
                a = m.TestFactory2(tag.pointer, 1)
                m.TestFactory1.__init__(a, tag.pointer)
            elif bad == 2:
                a = NotPybindDerived()
                m.TestFactory1.__init__(a, tag.pointer)

    # Same as above, but for a class with an alias:
    class BrokenTF6(m.TestFactory6):
        def __init__(self, bad):
            if bad == 1:
                a = m.TestFactory2(tag.pointer, 1)
                m.TestFactory6.__init__(a, tag.base, 1)
            elif bad == 2:
                a = m.TestFactory2(tag.pointer, 1)
                m.TestFactory6.__init__(a, tag.alias, 1)
            elif bad == 3:
                m.TestFactory6.__init__(NotPybindDerived.__new__(NotPybindDerived), tag.base, 1)
            elif bad == 4:
                m.TestFactory6.__init__(NotPybindDerived.__new__(NotPybindDerived), tag.alias, 1)

    for arg in (1, 2):
        with pytest.raises(TypeError) as excinfo:
            BrokenTF1(arg)
        assert str(excinfo.value) == "__init__(self, ...) called with invalid `self` argument"

    for arg in (1, 2, 3, 4):
        with pytest.raises(TypeError) as excinfo:
            BrokenTF6(arg)
        assert str(excinfo.value) == "__init__(self, ...) called with invalid `self` argument"
s="p">); std::string interface_modport = ""; for (auto &d : interface_modport_pool) { interface_modport = "\\" + d; } if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute("\\is_interface")) { // Check if the connected wire is a potential interface in the parent module std::string interface_name_str = conn.second.bits()[0].wire->name.str(); interface_name_str.replace(0,23,""); // Strip the prefix '$dummywireforinterface' from the dummy wire to get the name interface_name_str = "\\" + interface_name_str; RTLIL::IdString interface_name = interface_name_str; bool not_found_interface = false; if(module->get_bool_attribute("\\interfaces_replaced_in_module")) { // If 'interfaces' in the cell have not be been handled yet, there is no need to derive the sub-module either // Check if the interface instance is present in module: // Interface instances may either have the plain name or the name appended with '_inst_from_top_dummy'. // Check for both of them here int nexactmatch = interfaces_in_module.count(interface_name) > 0; std::string interface_name_str2 = interface_name_str + "_inst_from_top_dummy"; RTLIL::IdString interface_name2 = interface_name_str2; int nmatch2 = interfaces_in_module.count(interface_name2) > 0; if (nexactmatch > 0 || nmatch2 > 0) { if (nexactmatch != 0) // Choose the one with the plain name if it exists interface_name2 = interface_name; RTLIL::Module *mod_replace_ports = interfaces_in_module.at(interface_name2); for (auto &mod_wire : mod_replace_ports->wires_) { // Go over all wires in interface, and add replacements to lists. std::string signal_name1 = conn.first.str() + "." + log_id(mod_wire.first); std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire.first); connections_to_add_name.push_back(RTLIL::IdString(signal_name1)); if(module->wires_.count(signal_name2) == 0) { log_error("Could not find signal '%s' in '%s'\n", signal_name2.c_str(), log_id(module->name)); } else { RTLIL::Wire *wire_in_parent = module->wire(signal_name2); connections_to_add_signal.push_back(wire_in_parent); } } connections_to_remove.push_back(conn.first); interfaces_to_add_to_submodule[conn.first] = interfaces_in_module.at(interface_name2); // Add modports to a dict which will be passed to AstModule::derive if (interface_modport != "") { modports_used_in_submodule[conn.first] = interface_modport; } } else not_found_interface = true; } else not_found_interface = true; // If the interface instance has not already been derived in the module, we cannot complete at this stage. Set "has_interfaces_not_found" // which will delay the expansion of this cell: if (not_found_interface) { // If we have already gone over all cells in this module, and the interface has still not been found - flag it as an error: if(!(module->get_bool_attribute("\\cells_not_processed"))) { log_warning("Could not find interface instance for `%s' in `%s'\n", log_id(interface_name), log_id(module)); } else { // Only set has_interfaces_not_found if it would be possible to find them, since otherwiser we will end up in an infinite loop: has_interfaces_not_found = true; } } } } } // if (flag_check || flag_simcheck) { for (auto &conn : cell->connections()) { if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { int id = atoi(conn.first.c_str()+1); if (id <= 0 || id > GetSize(mod->ports)) log_error("Module `%s' referenced in module `%s' in cell `%s' has only %d ports, requested port %d.\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(mod->ports), id); } else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0) log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n", log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first)); } for (auto &param : cell->parameters) if (mod->avail_parameters.count(param.first) == 0 && param.first[0] != '$' && strchr(param.first.c_str(), '.') == NULL) log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a parameter named '%s'.\n", log_id(cell->type), log_id(module), log_id(cell), log_id(param.first)); } } RTLIL::Module *mod = design->modules_[cell->type]; if (design->modules_.at(cell->type)->get_blackbox_attribute()) { if (flag_simcheck) log_error("Module `%s' referenced in module `%s' in cell `%s' is a blackbox/whitebox module.\n", cell->type.c_str(), module->name.c_str(), cell->name.c_str()); continue; } // If interface instances not yet found, skip cell for now, and say we did something, so that we will return back here: if(has_interfaces_not_found) { did_something = true; // waiting for interfaces to be handled continue; } // Do the actual replacements of the SV interface port connection with the individual signal connections: for(unsigned int i=0;i<connections_to_add_name.size();i++) { cell->connections_[connections_to_add_name[i]] = connections_to_add_signal[i]; } // Remove the connection for the interface itself: for(unsigned int i=0;i<connections_to_remove.size();i++) { cell->connections_.erase(connections_to_remove[i]); } // If there are no overridden parameters AND not interfaces, then we can use the existing module instance as the type // for the cell: if (cell->parameters.size() == 0 && (interfaces_to_add_to_submodule.size() == 0 || !(cell->get_bool_attribute("\\module_not_derived")))) { // If the cell being processed is an the interface instance itself, go down to "handle_interface_instance:", // so that the signals of the interface are added to the parent module. if (mod->get_bool_attribute("\\is_interface")) { goto handle_interface_instance; } continue; } cell->type = mod->derive(design, cell->parameters, interfaces_to_add_to_submodule, modports_used_in_submodule); cell->parameters.clear(); did_something = true; handle_interface_instance: // We add all the signals of the interface explicitly to the parent module. This is always needed when we encounter // an interface instance: if (mod->get_bool_attribute("\\is_interface") && cell->get_bool_attribute("\\module_not_derived")) { cell->set_bool_attribute("\\is_interface"); RTLIL::Module *derived_module = design->modules_[cell->type]; interfaces_in_module[cell->name] = derived_module; did_something = true; } // We clear 'module_not_derived' such that we will not rederive the cell again (needed when there are interfaces connected to the cell) cell->attributes.erase("\\module_not_derived"); } // Clear the attribute 'cells_not_processed' such that it can be known that we // have been through all cells at least once, and that we can know whether // to flag an error because of interface instances not found: module->attributes.erase("\\cells_not_processed"); // If any interface instances or interface ports were found in the module, we need to rederive it completely: if ((interfaces_in_module.size() > 0 || has_interface_ports) && !module->get_bool_attribute("\\interfaces_replaced_in_module")) { module->reprocess_module(design, interfaces_in_module); return did_something; } for (auto &it : array_cells) { RTLIL::Cell *cell = it.first; int idx = it.second.first, num = it.second.second; if (design->modules_.count(cell->type) == 0) log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); RTLIL::Module *mod = design->modules_[cell->type]; for (auto &conn : cell->connections_) { int conn_size = conn.second.size(); RTLIL::IdString portname = conn.first; if (portname.begins_with("$")) { int port_id = atoi(portname.substr(1).c_str()); for (auto &wire_it : mod->wires_) if (wire_it.second->port_id == port_id) { portname = wire_it.first; break; } } if (mod->wires_.count(portname) == 0) log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); int port_size = mod->wires_.at(portname)->width; if (conn_size == port_size || conn_size == 0) continue; if (conn_size != port_size*num) log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); conn.second = conn.second.extract(port_size*idx, port_size); } } return did_something; } void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*, IdString::compare_ptr_by_name<Module>> &used, RTLIL::Module *mod, int indent) { if (used.count(mod) > 0) return; if (indent == 0) log("Top module: %s\n", mod->name.c_str()); else if (!mod->get_blackbox_attribute()) log("Used module: %*s%s\n", indent, "", mod->name.c_str()); used.insert(mod); for (auto cell : mod->cells()) { std::string celltype = cell->type.str(); if (celltype.compare(0, strlen("$array:"), "$array:") == 0) celltype = basic_cell_type(celltype); if (design->module(celltype)) hierarchy_worker(design, used, design->module(celltype), indent+4); } } void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib) { std::set<RTLIL::Module*, IdString::compare_ptr_by_name<Module>> used; hierarchy_worker(design, used, top, 0); std::vector<RTLIL::Module*> del_modules; for (auto &it : design->modules_) if (used.count(it.second) == 0) del_modules.push_back(it.second); else { // Now all interface ports must have been exploded, and it is hence // safe to delete all of the remaining dummy interface ports: pool<RTLIL::Wire*> del_wires; for(auto &wire : it.second->wires_) { if ((wire.second->port_input || wire.second->port_output) && wire.second->get_bool_attribute("\\is_interface")) { del_wires.insert(wire.second); } } if (del_wires.size() > 0) { it.second->remove(del_wires); it.second->fixup_ports(); } } int del_counter = 0; for (auto mod : del_modules) { if (!purge_lib && mod->get_blackbox_attribute()) continue; log("Removing unused module `%s'.\n", mod->name.c_str()); design->modules_.erase(mod->name); del_counter++; delete mod; } log("Removed %d unused modules.\n", del_counter); } bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) { if (cache.count(mod) == 0) for (auto c : mod->cells()) { RTLIL::Module *m = mod->design->module(c->type); if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$live", "$fair", "$cover")) return cache[mod] = true; } return cache[mod]; } int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db) { if (db.count(module) == 0) { int score = 0; db[module] = 0; for (auto cell : module->cells()) { std::string celltype = cell->type.str(); // Is this an array instance if (celltype.compare(0, strlen("$array:"), "$array:") == 0) celltype = basic_cell_type(celltype); // Is this cell a module instance? auto instModule = design->module(celltype); // If there is no instance for this, issue a warning. if (instModule != nullptr) { score = max(score, find_top_mod_score(design, instModule, db) + 1); } } db[module] = score; } return db.at(module); } RTLIL::Module *check_if_top_has_changed(Design *design, Module *top_mod) { if(top_mod != NULL && top_mod->get_bool_attribute("\\initial_top")) return top_mod; else { for (auto mod : design->modules()) { if (mod->get_bool_attribute("\\top")) { return mod; } } } return NULL; } struct HierarchyPass : public Pass { HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { } void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" hierarchy [-check] [-top <module>]\n"); log(" hierarchy -generate <cell-types> <port-decls>\n"); log("\n"); log("In parametric designs, a module might exists in several variations with\n"); log("different parameter values. This pass looks at all modules in the current\n"); log("design an re-runs the language frontends for the parametric modules as\n"); log("needed. It also resolves assignments to wired logic data types (wand/wor),\n"); log("resolves positional module parameters, unroll array instances, and more.\n"); log("\n"); log(" -check\n"); log(" also check the design hierarchy. this generates an error when\n"); log(" an unknown module is used as cell type.\n"); log("\n"); log(" -simcheck\n"); log(" like -check, but also throw an error if blackbox modules are\n"); log(" instantiated, and throw an error if the design has no top module.\n"); log("\n"); log(" -purge_lib\n"); log(" by default the hierarchy command will not remove library (blackbox)\n"); log(" modules. use this option to also remove unused blackbox modules.\n"); log("\n"); log(" -libdir <directory>\n"); log(" search for files named <module_name>.v in the specified directory\n"); log(" for unknown modules and automatically run read_verilog for each\n"); log(" unknown module.\n"); log("\n"); log(" -keep_positionals\n"); log(" per default this pass also converts positional arguments in cells\n"); log(" to arguments using port names. This option disables this behavior.\n"); log("\n"); log(" -keep_portwidths\n"); log(" per default this pass adjusts the port width on cells that are\n"); log(" module instances when the width does not match the module port. This\n"); log(" option disables this behavior.\n"); log("\n"); log(" -nodefaults\n"); log(" do not resolve input port default values\n"); log("\n"); log(" -nokeep_asserts\n"); log(" per default this pass sets the \"keep\" attribute on all modules\n"); log(" that directly or indirectly contain one or more formal properties.\n"); log(" This option disables this behavior.\n"); log("\n"); log(" -top <module>\n"); log(" use the specified top module to build the design hierarchy. Modules\n"); log(" outside this tree (unused modules) are removed.\n"); log("\n"); log(" when the -top option is used, the 'top' attribute will be set on the\n"); log(" specified top module. otherwise a module with the 'top' attribute set\n"); log(" will implicitly be used as top module, if such a module exists.\n"); log("\n"); log(" -auto-top\n"); log(" automatically determine the top of the design hierarchy and mark it.\n"); log("\n"); log(" -chparam name value \n"); log(" elaborate the top module using this parameter value. Modules on which\n"); log(" this parameter does not exist may cause a warning message to be output.\n"); log(" This option can be specified multiple times to override multiple\n"); log(" parameters. String values must be passed in double quotes (\").\n"); log("\n"); log("In -generate mode this pass generates blackbox modules for the given cell\n"); log("types (wildcards supported). For this the design is searched for cells that\n"); log("match the given types and then the given port declarations are used to\n"); log("determine the direction of the ports. The syntax for a port declaration is:\n"); log("\n"); log(" {i|o|io}[@<num>]:<portname>\n"); log("\n"); log("Input ports are specified with the 'i' prefix, output ports with the 'o'\n"); log("prefix and inout ports with the 'io' prefix. The optional <num> specifies\n"); log("the position of the port in the parameter list (needed when instantiated\n"); log("using positional arguments). When <num> is not specified, the <portname> can\n"); log("also contain wildcard characters.\n"); log("\n"); log("This pass ignores the current selection and always operates on all modules\n"); log("in the current design.\n"); log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n"); bool flag_check = false; bool flag_simcheck = false; bool purge_lib = false; RTLIL::Module *top_mod = NULL; std::string load_top_mod; std::vector<std::string> libdirs; bool auto_top_mode = false; bool generate_mode = false; bool keep_positionals = false; bool keep_portwidths = false; bool nodefaults = false; bool nokeep_asserts = false; std::vector<std::string> generate_cells; std::vector<generate_port_decl_t> generate_ports; std::map<std::string, std::string> parameters; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-generate" && !flag_check && !flag_simcheck && !top_mod) { generate_mode = true; log("Entering generate mode.\n"); while (++argidx < args.size()) { const char *p = args[argidx].c_str(); generate_port_decl_t decl; if (p[0] == 'i' && p[1] == 'o') decl.input = true, decl.output = true, p += 2; else if (*p == 'i') decl.input = true, decl.output = false, p++; else if (*p == 'o') decl.input = false, decl.output = true, p++; else goto is_celltype; if (*p == '@') { char *endptr; decl.index = strtol(++p, &endptr, 10); if (decl.index < 1) goto is_celltype; p = endptr; } else decl.index = 0; if (*(p++) != ':') goto is_celltype; if (*p == 0) goto is_celltype; decl.portname = p; log("Port declaration: %s", decl.input ? decl.output ? "inout" : "input" : "output"); if (decl.index >= 1) log(" [at position %d]", decl.index); log(" %s\n", decl.portname.c_str()); generate_ports.push_back(decl); continue; is_celltype: log("Celltype: %s\n", args[argidx].c_str()); generate_cells.push_back(RTLIL::unescape_id(args[argidx])); } continue; } if (args[argidx] == "-check") { flag_check = true; continue; } if (args[argidx] == "-simcheck") { flag_simcheck = true; continue; } if (args[argidx] == "-purge_lib") { purge_lib = true; continue; } if (args[argidx] == "-keep_positionals") { keep_positionals = true; continue; } if (args[argidx] == "-keep_portwidths") { keep_portwidths = true; continue; } if (args[argidx] == "-nodefaults") { nodefaults = true; continue; } if (args[argidx] == "-nokeep_asserts") { nokeep_asserts = true; continue; } if (args[argidx] == "-libdir" && argidx+1 < args.size()) { libdirs.push_back(args[++argidx]); continue; } if (args[argidx] == "-top") { if (++argidx >= args.size()) log_cmd_error("Option -top requires an additional argument!\n"); load_top_mod = args[argidx]; continue; } if (args[argidx] == "-auto-top") { auto_top_mode = true; continue; } if (args[argidx] == "-chparam" && argidx+2 < args.size()) { const std::string &key = args[++argidx]; const std::string &value = args[++argidx]; auto r = parameters.emplace(key, value); if (!r.second) { log_warning("-chparam %s already specified: overwriting.\n", key.c_str()); r.first->second = value; } continue; } break; } extra_args(args, argidx, design, false); if (!load_top_mod.empty()) { IdString top_name = RTLIL::escape_id(load_top_mod); IdString abstract_id = "$abstract" + RTLIL::escape_id(load_top_mod); top_mod = design->module(top_name); dict<RTLIL::IdString, RTLIL::Const> top_parameters; for (auto &para : parameters) { SigSpec sig_value; if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second)) log_cmd_error("Can't decode value '%s'!\n", para.second.c_str()); top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const(); } if (top_mod == nullptr && design->module(abstract_id)) top_mod = design->module(design->module(abstract_id)->derive(design, top_parameters)); else if (top_mod != nullptr && !top_parameters.empty()) top_mod = design->module(top_mod->derive(design, top_parameters)); if (top_mod != nullptr && top_mod->name != top_name) { Module *m = top_mod->clone(); m->name = top_name; Module *old_mod = design->module(top_name); if (old_mod) design->remove(old_mod); design->add(m); top_mod = m; } } if (top_mod == nullptr && !load_top_mod.empty()) { #ifdef YOSYS_ENABLE_VERIFIC if (verific_import_pending) { verific_import(design, parameters, load_top_mod); top_mod = design->module(RTLIL::escape_id(load_top_mod)); } #endif if (top_mod == NULL) log_cmd_error("Module `%s' not found!\n", load_top_mod.c_str()); } else { #ifdef YOSYS_ENABLE_VERIFIC if (verific_import_pending) verific_import(design, parameters); #endif } if (generate_mode) { generate(design, generate_cells, generate_ports); return; } log_push(); if (top_mod == nullptr) for (auto &mod_it : design->modules_) if (mod_it.second->get_bool_attribute("\\top")) top_mod = mod_it.second; if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) { IdString top_name = top_mod->name.substr(strlen("$abstract")); dict<RTLIL::IdString, RTLIL::Const> top_parameters; for (auto &para : parameters) { SigSpec sig_value; if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second)) log_cmd_error("Can't decode value '%s'!\n", para.second.c_str()); top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const(); } top_mod = design->module(top_mod->derive(design, top_parameters)); if (top_mod != nullptr && top_mod->name != top_name) { Module *m = top_mod->clone(); m->name = top_name; Module *old_mod = design->module(top_name); if (old_mod) design->remove(old_mod); design->add(m); top_mod = m; } } if (top_mod == nullptr && auto_top_mode) { log_header(design, "Finding top of design hierarchy..\n"); dict<Module*, int> db; for (Module *mod : design->selected_modules()) { int score = find_top_mod_score(design, mod, db); log("root of %3d design levels: %-20s\n", score, log_id(mod)); if (!top_mod || score > db[top_mod]) top_mod = mod; } if (top_mod != nullptr) log("Automatically selected %s as design top module.\n", log_id(top_mod)); } if (flag_simcheck && top_mod == nullptr) log_error("Design has no top module.\n"); if (top_mod != NULL) { for (auto &mod_it : design->modules_) if (mod_it.second == top_mod) mod_it.second->attributes["\\initial_top"] = RTLIL::Const(1); else mod_it.second->attributes.erase("\\initial_top"); } bool did_something = true; while (did_something) { did_something = false; std::set<RTLIL::Module*, IdString::compare_ptr_by_name<Module>> used_modules; if (top_mod != NULL) { log_header(design, "Analyzing design hierarchy..\n"); hierarchy_worker(design, used_modules, top_mod, 0); } else { for (auto mod : design->modules()) used_modules.insert(mod); } for (auto module : used_modules) { if (expand_module(design, module, flag_check, flag_simcheck, libdirs)) did_something = true; } // The top module might have changed if interface instances have been detected in it: RTLIL::Module *tmp_top_mod = check_if_top_has_changed(design, top_mod); if (tmp_top_mod != NULL) { if (tmp_top_mod != top_mod){ top_mod = tmp_top_mod; did_something = true; } } // Delete modules marked as 'to_delete': std::vector<RTLIL::Module *> modules_to_delete; for(auto &mod_it : design->modules_) { if (mod_it.second->get_bool_attribute("\\to_delete")) { modules_to_delete.push_back(mod_it.second); } } for(size_t i=0; i<modules_to_delete.size(); i++) { design->remove(modules_to_delete[i]); } } if (top_mod != NULL) { log_header(design, "Analyzing design hierarchy..\n"); hierarchy_clean(design, top_mod, purge_lib); } if (top_mod != NULL) { for (auto &mod_it : design->modules_) { if (mod_it.second == top_mod) mod_it.second->attributes["\\top"] = RTLIL::Const(1); else mod_it.second->attributes.erase("\\top"); mod_it.second->attributes.erase("\\initial_top"); } } if (!nokeep_asserts) { std::map<RTLIL::Module*, bool> cache; for (auto mod : design->modules()) if (set_keep_assert(cache, mod)) { log("Module %s directly or indirectly contains formal properties -> setting \"keep\" attribute.\n", log_id(mod)); mod->set_bool_attribute("\\keep"); } } if (!keep_positionals) { std::set<RTLIL::Module*> pos_mods; std::map<std::pair<RTLIL::Module*,int>, RTLIL::IdString> pos_map; std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work; for (auto &mod_it : design->modules_) for (auto &cell_it : mod_it.second->cells_) { RTLIL::Cell *cell = cell_it.second; if (design->modules_.count(cell->type) == 0) continue; for (auto &conn : cell->connections()) if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { pos_mods.insert(design->modules_.at(cell->type)); pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod_it.second, cell)); break; } } for (auto module : pos_mods) for (auto &wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id > 0) pos_map[std::pair<RTLIL::Module*,int>(module, wire->port_id)] = wire->name; } for (auto &work : pos_work) { RTLIL::Module *module = work.first; RTLIL::Cell *cell = work.second; log("Mapping positional arguments of cell %s.%s (%s).\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); dict<RTLIL::IdString, RTLIL::SigSpec> new_connections; for (auto &conn : cell->connections()) if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { int id = atoi(conn.first.c_str()+1); std::pair<RTLIL::Module*,int> key(design->modules_.at(cell->type), id); if (pos_map.count(key) == 0) { log(" Failed to map positional argument %d of cell %s.%s (%s).\n", id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); new_connections[conn.first] = conn.second; } else new_connections[pos_map.at(key)] = conn.second; } else new_connections[conn.first] = conn.second; cell->connections_ = new_connections; } } if (!nodefaults) { dict<IdString, dict<IdString, Const>> defaults_db; for (auto module : design->modules()) for (auto wire : module->wires()) if (wire->port_input && wire->attributes.count("\\defaultvalue")) defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue"); for (auto module : design->modules()) for (auto cell : module->cells()) { if (defaults_db.count(cell->type) == 0) continue; if (keep_positionals) { bool found_positionals = false; for (auto &conn : cell->connections()) if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') found_positionals = true; if (found_positionals) continue; } for (auto &it : defaults_db.at(cell->type)) if (!cell->hasPort(it.first)) cell->setPort(it.first, it.second); } } std::set<Module*> blackbox_derivatives; std::vector<Module*> design_modules = design->modules(); for (auto module : design_modules) { pool<Wire*> wand_wor_index; dict<Wire*, SigSpec> wand_map, wor_map; vector<SigSig> new_connections; for (auto wire : module->wires()) { if (wire->get_bool_attribute("\\wand")) { wand_map[wire] = SigSpec(); wand_wor_index.insert(wire); } if (wire->get_bool_attribute("\\wor")) { wor_map[wire] = SigSpec(); wand_wor_index.insert(wire); } } for (auto &conn : module->connections()) { SigSig new_conn; int cursor = 0; for (auto c : conn.first.chunks()) { Wire *w = c.wire; SigSpec rhs = conn.second.extract(cursor, GetSize(c)); if (wand_wor_index.count(w) == 0) { new_conn.first.append(c); new_conn.second.append(rhs); } else { if (wand_map.count(w)) { SigSpec sig = SigSpec(State::S1, GetSize(w)); sig.replace(c.offset, rhs); wand_map.at(w).append(sig); } else { SigSpec sig = SigSpec(State::S0, GetSize(w)); sig.replace(c.offset, rhs); wor_map.at(w).append(sig); } } cursor += GetSize(c); } new_connections.push_back(new_conn); } module->new_connections(new_connections); for (auto cell : module->cells()) { if (!cell->known()) continue; for (auto &conn : cell->connections()) { if (!cell->output(conn.first)) continue; SigSpec new_sig; bool update_port = false; for (auto c : conn.second.chunks()) { Wire *w = c.wire; if (wand_wor_index.count(w) == 0) { new_sig.append(c); continue; } Wire *t = module->addWire(NEW_ID, GetSize(c)); new_sig.append(t); update_port = true; if (wand_map.count(w)) { SigSpec sig = SigSpec(State::S1, GetSize(w)); sig.replace(c.offset, t); wand_map.at(w).append(sig); } else { SigSpec sig = SigSpec(State::S0, GetSize(w)); sig.replace(c.offset, t); wor_map.at(w).append(sig); } } if (update_port) cell->setPort(conn.first, new_sig); } } for (auto w : wand_wor_index) { bool wand = wand_map.count(w); SigSpec sigs = wand ? wand_map.at(w) : wor_map.at(w); if (GetSize(sigs) == 0) continue; if (GetSize(w) == 1) { if (wand) module->addReduceAnd(NEW_ID, sigs, w); else module->addReduceOr(NEW_ID, sigs, w); continue; } SigSpec s = sigs.extract(0, GetSize(w)); for (int i = GetSize(w); i < GetSize(sigs); i += GetSize(w)) { if (wand) s = module->And(NEW_ID, s, sigs.extract(i, GetSize(w))); else s = module->Or(NEW_ID, s, sigs.extract(i, GetSize(w))); } module->connect(w, s); } for (auto cell : module->cells()) { Module *m = design->module(cell->type); if (m == nullptr) continue; if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) { IdString new_m_name = m->derive(design, cell->parameters, true); if (new_m_name.empty()) continue; if (new_m_name != m->name) { m = design->module(new_m_name); blackbox_derivatives.insert(m); } } for (auto &conn : cell->connections()) { Wire *w = m->wire(conn.first); if (w == nullptr || w->port_id == 0) continue; if (GetSize(conn.second) == 0) continue; SigSpec sig = conn.second; if (!keep_portwidths && GetSize(w) != GetSize(conn.second)) { if (GetSize(w) < GetSize(conn.second)) { int n = GetSize(conn.second) - GetSize(w); if (!w->port_input && w->port_output) module->connect(sig.extract(GetSize(w), n), Const(0, n)); sig.remove(GetSize(w), n); } else { int n = GetSize(w) - GetSize(conn.second); if (w->port_input && !w->port_output) sig.append(Const(0, n)); else sig.append(module->addWire(NEW_ID, n)); } if (!conn.second.is_fully_const() || !w->port_input || w->port_output) log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell), log_id(conn.first), GetSize(conn.second), GetSize(sig)); cell->setPort(conn.first, sig); } if (w->port_output && !w->port_input && sig.has_const()) log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n", log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig)); } } } for (auto module : blackbox_derivatives) design->remove(module); log_pop(); } } HierarchyPass; PRIVATE_NAMESPACE_END