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* ice40/pll: Fix typo when testing for global port output netSylvain Munaut2018-11-201-1/+1
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add support for SB_RGBA_DRVSylvain Munaut2018-11-195-2/+58
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add global network output support for LFOSC/HFOSCSylvain Munaut2018-11-191-2/+10
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/pack: Add helper to constain cells that are unique in the FPGASylvain Munaut2018-11-191-0/+16
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add support for SB_GB_IOSylvain Munaut2018-11-195-8/+31
| | | | | | | | | | During packing we replace them by standard SB_IO cells and create the 'fake' SB_GB that matches that IO site global buffer connection. It's done in a separate pass because we need to make sure the nextpnr iob have been dealt first so we have our final Bel location on the SB_IO. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add support for PLL global outputs via PADINSylvain Munaut2018-11-192-84/+73
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Introduce the concept of forPadIn SB_GBSylvain Munaut2018-11-195-2/+53
| | | | | | | | | | | | | | Those are cells that are created mainly to handle the various sources a global network can be driven from other than a user net. When the flag is set, this means the global network usually driven by this BEL is in fact driven by something else and so that SB_GB BEL and matching global network can't be used. This is also what gets used to set the extra bits during bitstream generation. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/chipdb: Add wires to global network for all cells that can drive itSylvain Munaut2018-11-193-6/+22
| | | | | | | | The icebox DB is a bit inconsistent in how global network connections are represented. Here we make it appear consistent by creating ports on the cells that can drive it. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add GlobalNetowkrInfo in the chip databaseSylvain Munaut2018-11-192-37/+63
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Fix BEL validity check for PLL vs SB_IOSylvain Munaut2018-11-191-21/+20
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Improve the is_sb_pll40_XXX predicates collectionSylvain Munaut2018-11-191-1/+13
| | | | | | | | | - Add a test for dual output PLL variant - Make them handle the packet version of the cell This will become useful for various tests during PLL rework Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Fix PLLTYPE for SB_PLL40_2F_PADSylvain Munaut2018-11-191-1/+1
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributesSylvain Munaut2018-11-191-0/+18
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Make PLL default FEEDBACK_MODE to SIMPLESylvain Munaut2018-11-191-1/+1
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Minor fix in predicate checking for logic portSylvain Munaut2018-11-191-2/+3
| | | | | | | - is_sb_pll40 covers all the PLL types - Use helper to test for gbuf Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/pack: Stop looking for BEL when we have one during PLL placementSylvain Munaut2018-11-191-0/+1
| | | | | | | Ideally we should first process all the PLL that are constrained somehow (either explicitely or because they are PAD) and then free place the rest. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/pack: Allow PLL to be constrained via 'BEL' attributesSylvain Munaut2018-11-191-0/+10
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/pack: Make sure we don't use a LOCKED bel when placing PLLSylvain Munaut2018-11-191-0/+2
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/arch: Add helper to check if a BEL is LOCKED or notSylvain Munaut2018-11-192-0/+21
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/chipdb: Fix LOCKED keyword support to include all packagesSylvain Munaut2018-11-191-1/+2
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IOSylvain Munaut2018-11-191-2/+7
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhereSylvain Munaut2018-11-161-0/+5
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/bitstream: Convert to UNIX line endingsSylvain Munaut2018-11-161-1043/+1043
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* clangformatDavid Shah2018-11-161-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Remove unnecessary RAM assertionDavid Shah2018-11-161-1/+0
| | | | | | Fixes #121 Signed-off-by: David Shah <dave@ds0.me>
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-132-4/+5
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| * [ice40] getBudgetOverride() to use constrained Z not placed ZEddie Hung2018-11-132-4/+5
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* | Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-133-18/+41
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| * Merge pull request #107 from YosysHQ/router_improveEddie Hung2018-11-132-17/+40
| |\ | | | | | | Major rewrite of "router1"
| | * Various router1 fixes, Add BelId/WireId/PipId::operator<()Clifford Wolf2018-11-131-0/+3
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * clangformatClifford Wolf2018-11-111-4/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add getConflictingWireWire() arch API, streamline getConflictingXY semanticClifford Wolf2018-11-111-14/+29
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add getConflictingPipWire() arch API, router1 improvementsClifford Wolf2018-11-111-9/+17
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Mark getArchOptions as override in derived classesPedro Vanzella2018-11-131-1/+1
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* | | timing: Add support for clock constraintsDavid Shah2018-11-122-0/+12
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | archapi: Add getDelayFromNS to improve timing algorithm portabilityDavid Shah2018-11-121-0/+6
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | timing: Fix handling of clock inputsDavid Shah2018-11-121-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Working on multi-clock analysisDavid Shah2018-11-121-6/+4
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | timing: iCE40 Arch API changes for clocking infoDavid Shah2018-11-123-21/+68
|/ / | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ice40: Don't set colbuf bits for 384David Shah2018-11-111-0/+2
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Merge pull request #93 from YosysHQ/gui_changesMiodrag Milanović2018-11-101-2/+2
|\ \ | |/ |/| Gui changes
| * fix grid dimensions for ice40Miodrag Milanovic2018-10-271-2/+2
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* | ice40: Fix SPRAM and IO globalsDavid Shah2018-11-041-0/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ice40: Fix PLL DYNAMICDELAYDavid Shah2018-10-271-1/+2
|/ | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ups, uncommentMiodrag Milanovic2018-10-271-2/+2
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* Fixed pip graphicsMiodrag Milanovic2018-10-271-4/+4
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* Merge pull request #88 from YosysHQ/issue72Eddie Hung2018-10-111-6/+13
|\ | | | | Resolve issue #72
| * [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNOREEddie Hung2018-09-151-6/+13
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* | Add info message for promoted global netsClifford Wolf2018-10-031-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | ice40: Add error for bad PACKAGE_PIN connectionsDavid Shah2018-10-031-2/+13
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
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