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* | | timing: Fix handling of clock inputsDavid Shah2018-11-121-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Working on multi-clock analysisDavid Shah2018-11-121-6/+4
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | timing: iCE40 Arch API changes for clocking infoDavid Shah2018-11-123-21/+68
|/ / | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ice40: Don't set colbuf bits for 384David Shah2018-11-111-0/+2
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Merge pull request #93 from YosysHQ/gui_changesMiodrag Milanović2018-11-101-2/+2
|\ \ | |/ |/| Gui changes
| * fix grid dimensions for ice40Miodrag Milanovic2018-10-271-2/+2
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* | ice40: Fix SPRAM and IO globalsDavid Shah2018-11-041-0/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ice40: Fix PLL DYNAMICDELAYDavid Shah2018-10-271-1/+2
|/ | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ups, uncommentMiodrag Milanovic2018-10-271-2/+2
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* Fixed pip graphicsMiodrag Milanovic2018-10-271-4/+4
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* Merge pull request #88 from YosysHQ/issue72Eddie Hung2018-10-111-6/+13
|\ | | | | Resolve issue #72
| * [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNOREEddie Hung2018-09-151-6/+13
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* | Add info message for promoted global netsClifford Wolf2018-10-031-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | ice40: Add error for bad PACKAGE_PIN connectionsDavid Shah2018-10-031-2/+13
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Refactor chain finder to its own fileDavid Shah2018-09-301-39/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | clangformatDavid Shah2018-09-308-28/+34
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Merge pull request #79 from YosysHQ/ice40lvdsClifford Wolf2018-09-258-13/+88
|\ \ | | | | | | ice40: Adding LVDS input support
| * | ice40: LVDS input bitstream supportDavid Shah2018-09-241-4/+48
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | ice40: Tristate IO support fixesDavid Shah2018-09-243-6/+10
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | ice40: Validity check for LVDS IODavid Shah2018-09-244-0/+29
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | ice40: Remove obsolete belType memberDavid Shah2018-09-243-3/+1
| |/ | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Merge pull request #76 from YosysHQ/plloutglobal_fixClifford Wolf2018-09-252-2/+38
|\ \ | | | | | | Add needed PLLOUTGLOBAL ports and mapped it
| * | Added required checks for PLL and fixed messages eolMiodrag Milanovic2018-09-191-3/+31
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| * | Add needed PLLOUTGLOBAL ports and mapped it properlyMiodrag Milanovic2018-09-122-0/+8
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* / ice40: Fix carry packer bugDavid Shah2018-09-251-2/+2
|/ | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Merge pull request #56 from YosysHQ/q3k/issue-55Serge Bazanski2018-08-192-12/+28
|\ | | | | ice40: make PLL packing more robust
| * ice40: make PLL packing more robustSergiusz Bazanski2018-08-192-12/+28
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* | Add more missing iCE40 gfx (LP/HX is complete now)Clifford Wolf2018-08-193-4/+47
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add iCE40 gfx for carry chain pips and LUT cascade pipsClifford Wolf2018-08-191-5/+43
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix iCE40 pip gfx for pips on the top edge of a switchboxClifford Wolf2018-08-191-5/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add iCE40 gfx for IO span-4 cornersClifford Wolf2018-08-193-3/+36
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add iCE40 gfx for span-4 wires between IO tilesClifford Wolf2018-08-195-7/+126
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #47 from YosysHQ/settings_propagateClifford Wolf2018-08-184-16/+5
|\ | | | | Use settings for placer1 and router1
| * Save settings and give nicer names to someMiodrag Milanovic2018-08-102-3/+3
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| * Use settings for placer1 and router1Miodrag Milanovic2018-08-092-13/+2
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* | Add iCE40 gfx for wires connecting fabric tiles and IO tilesClifford Wolf2018-08-184-2/+261
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve iCE40 gfx for IO tiles and RAM tilesClifford Wolf2018-08-185-23/+243
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add ice40 wire attributes (grid position, segment list)Clifford Wolf2018-08-183-18/+45
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge branch 'master' of github.com:YosysHQ/nextpnr into archattrClifford Wolf2018-08-181-4/+6
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| * | do not break if there are no nets loaded from sym sectionMiodrag Milanovic2018-08-181-4/+6
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* | | Add Arch attrs APIClifford Wolf2018-08-141-0/+18
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge remote-tracking branch 'origin/master' into placer_speedupEddie Hung2018-08-101-1/+11
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| * Merge pull request #42 from YosysHQ/floorplanDavid Shah2018-08-091-1/+11
| |\ | | | | | | Add basic data structures for floorplanning
| | * Add pip locationsClifford Wolf2018-08-091-1/+11
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of ↵Eddie Hung2018-08-103-17/+18
| | | | | | | | | | | | std::array
* | | Make containers staticEddie Hung2018-08-091-5/+7
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* | ice40: Speedup Arch::predictDelay() with pass-by-refEddie Hung2018-08-081-1/+1
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* | Use settings for json and pcfMiodrag Milanovic2018-08-084-8/+12
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* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-085-389/+270
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| * Merge pull request #44 from YosysHQ/improve_timing_specDavid Shah2018-08-082-32/+89
| |\ | | | | | | Speed up budget allocator using topographical ordering and update cell timing API
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