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* Set the default log to stdoutZipCPU2018-06-072-2/+17
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| * Moved placer definitions to place.h, main automatically runs placer nowZipCPU2018-06-071-3/+2
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| * Initial (random) placer capabilityZipCPU2018-06-071-1/+12
| | | | | | | | | | | | | | | | | | | | This commit also includes changes to jsonparse to allow it to 1) recognize ports with no connection, and set their net pointers to NULL 2) recognize designs with a ports node rather than a ports_direction The rule checker has also been modified to accommodate possible NULL netlists The ice40 chip now also has iterator operations ++bi and bi++.
| * Preliminary placer changes to mainZipCPU2018-06-071-0/+7
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* | ice40: More Python bindings and examplesDavid Shah2018-06-072-1/+17
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ice40: Refactor PortPin and add Python bindingDavid Shah2018-06-075-318/+126
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Connected the log file facility to stderrZipCPU2018-06-071-0/+3
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* cmake: Add HX1K-only builds supportDavid Shah2018-06-071-1/+9
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Reformat Python bindings and ice40 mainDavid Shah2018-06-072-225/+230
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Fixing file->run renamingDavid Shah2018-06-071-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrDavid Shah2018-06-073-813/+819
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| * clang-format for design and chip codebaseClifford Wolf2018-06-072-813/+817
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix clang-format include order issuesClifford Wolf2018-06-071-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge branch 'python'David Shah2018-06-071-1/+2
|\ \ | |/ |/| | | Signed-off-by: David Shah <davey1576@gmail.com>
| * Global design object workingDavid Shah2018-06-071-1/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * Working on global Python design objectDavid Shah2018-06-071-0/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Add ICE40_HX1K_ONLY config macroClifford Wolf2018-06-072-8/+43
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Rename --file to --runClifford Wolf2018-06-071-3/+3
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Allow specifying multiple Python files on the command lineDavid Shah2018-06-071-3/+4
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Allow loading and running Python files before GUI startsDavid Shah2018-06-071-14/+15
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Attempt to add JSON parser--not working yet w/ build systemZipCPU2018-06-061-12/+26
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* Add iCE40 device selection, improve iCE40 IO GraphicElementsClifford Wolf2018-06-062-13/+61
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add simple SVG generator to ice40 mainClifford Wolf2018-06-061-4/+36
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add ice40 geometry informationClifford Wolf2018-06-063-15/+95
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add ice40 --test modeClifford Wolf2018-06-062-5/+66
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor Chip API and iCE40 databaseClifford Wolf2018-06-064-166/+376
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Initial GUI workMiodrag Milanovic2018-06-051-7/+75
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* Initial JSON parserZipCPU2018-06-051-0/+3
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* Add iCE40 blockram belsClifford Wolf2018-06-043-0/+285
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Replace GuiLine with GraphicElementClifford Wolf2018-06-041-7/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add iCE40 SB_IO belsClifford Wolf2018-06-033-26/+106
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add ice40 ICESTORM_LC belsClifford Wolf2018-06-023-12/+157
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove now obsolete ice40/makefile.incClifford Wolf2018-06-021-17/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix race condition and optimise the buildDavid Shah2018-06-022-2/+7
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* Python bindings working on both architecturesDavid Shah2018-06-021-9/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Simple Python test workingDavid Shah2018-06-021-0/+37
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add architecture specific Python defsDavid Shah2018-06-021-0/+27
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add a CMake based build systemDavid Shah2018-06-021-0/+14
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Use singular in type names (BelRange, WireIterator)Clifford Wolf2018-06-021-18/+18
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add iCE40 blinky exampleClifford Wolf2018-05-313-0/+152
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add DelayInfo structClifford Wolf2018-05-291-2/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Progress in chip.h APIClifford Wolf2018-05-262-32/+174
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Progress in ice40 chipdbClifford Wolf2018-05-264-52/+131
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Start work on iCE40 chipdbClifford Wolf2018-05-266-0/+423
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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