| Commit message (Expand) | Author | Age | Files | Lines |
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| * | ice40: Fix getBelsByTile | David Shah | 2020-06-29 | 1 | -1/+1 |
| * | Simplify and improve chipdb embedding/loading. | whitequark | 2020-06-26 | 1 | -0/+2 |
| * | ice40: Fix DSP cascade wires | David Shah | 2019-09-03 | 1 | -4/+9 |
| * | ice40: add RGB_DRV/LED_DRV_CUR support for u4k | Simon Schubert | 2019-06-10 | 1 | -0/+2 |
| * | ice40: u4k merge fix | David Shah | 2019-02-25 | 1 | -0/+2 |
| * | Merge pull request #239 from YosysHQ/dsp_casc_dummy_wires | David Shah | 2019-02-25 | 1 | -0/+19 |
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| | * | ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O ports | David Shah | 2019-02-21 | 1 | -0/+19 |
| * | | ice40: support u4k | Simon Schubert | 2019-02-23 | 1 | -1/+1 |
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| * | ice40/chipdb: Add wires to global network for all cells that can drive it | Sylvain Munaut | 2018-11-19 | 1 | -4/+18 |
| * | ice40: Add GlobalNetowkrInfo in the chip database | Sylvain Munaut | 2018-11-19 | 1 | -36/+46 |
| * | ice40/chipdb: Fix LOCKED keyword support to include all packages | Sylvain Munaut | 2018-11-19 | 1 | -1/+2 |
| * | Add more missing iCE40 gfx (LP/HX is complete now) | Clifford Wolf | 2018-08-19 | 1 | -4/+0 |
| * | Add iCE40 gfx for span-4 wires between IO tiles | Clifford Wolf | 2018-08-19 | 1 | -2/+0 |
| * | Add iCE40 gfx for wires connecting fabric tiles and IO tiles | Clifford Wolf | 2018-08-18 | 1 | -0/+7 |
| * | Improve iCE40 gfx for IO tiles and RAM tiles | Clifford Wolf | 2018-08-18 | 1 | -21/+179 |
| * | Add ice40 wire attributes (grid position, segment list) | Clifford Wolf | 2018-08-18 | 1 | -0/+7 |
| * | Get rid of old iCE40 id_ Arch members | Clifford Wolf | 2018-08-08 | 1 | -0/+2 |
| * | Get rid of PortPin and BelType (ice40, generic, docs) | Clifford Wolf | 2018-08-08 | 1 | -40/+34 |
| * | Add new iCE40 delay estimator and delay predictor | Clifford Wolf | 2018-08-04 | 1 | -1/+1 |
| * | Fix bug in ice40 chipdby.py add_wire() that moves some wires to X0/Y0 | Clifford Wolf | 2018-08-04 | 1 | -3/+7 |
| * | Merge branch 'master' of github.com:YosysHQ/nextpnr into lutperm | Clifford Wolf | 2018-08-04 | 1 | -1/+5 |
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| | * | ice40: Add SB_GB timing to database | David Shah | 2018-08-04 | 1 | -1/+5 |
| * | | Proper ice40 wire types | Clifford Wolf | 2018-08-03 | 1 | -42/+93 |
| * | | Add iCE40 pseudo-pips for lut permutation | Clifford Wolf | 2018-08-03 | 1 | -12/+35 |
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| * | Merge pull request #22 from YosysHQ/routethru | Clifford Wolf | 2018-08-03 | 1 | -3/+38 |
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| | * | Add LUT route-through pips to iCE40 architecture database | Clifford Wolf | 2018-08-02 | 1 | -3/+38 |
| * | | ice40: Use real cell timings | David Shah | 2018-08-02 | 1 | -5/+6 |
| * | | ice40: Adding cell timings to chipdb | David Shah | 2018-08-02 | 1 | -0/+72 |
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| * | Use icestorm timing information | Clifford Wolf | 2018-07-31 | 1 | -27/+42 |
| * | Add binary search to getBelPinWire() and getBelPinType() | Clifford Wolf | 2018-07-31 | 1 | -8/+6 |
| * | Towards better ice40 timing data | Clifford Wolf | 2018-07-30 | 1 | -7/+21 |
| * | cmake: Set --fast and --slow chipdb.py arguments | David Shah | 2018-07-30 | 1 | -1/+1 |
| * | Add ice40 chipdb.py --fast/--slow | Clifford Wolf | 2018-07-30 | 1 | -0/+30 |
| * | Add iCE40 fast/slow delay fields to chipdb | Clifford Wolf | 2018-07-30 | 1 | -3/+9 |
| * | Improvements in bbasm | Clifford Wolf | 2018-07-26 | 1 | -1/+2 |
| * | Use bbasm to create iCE40 chipdb | Clifford Wolf | 2018-07-24 | 1 | -273/+38 |
| * | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pll | Sergiusz Bazanski | 2018-07-24 | 1 | -37/+1 |
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| | * | Remove uphill/downhill bel pins from ice40 db | Clifford Wolf | 2018-07-24 | 1 | -30/+0 |
| | * | ice40: Fix SPRAM and other primitives in corners other than (0, 0) | David Shah | 2018-07-24 | 1 | -1/+1 |
| * | | ice40: move PLL->IO from pseudo pip to second uphill bel | Sergiusz Bazanski | 2018-07-24 | 1 | -35/+3 |
| * | | ice40: emit list of upbels in chipdb | Sergiusz Bazanski | 2018-07-24 | 1 | -12/+18 |
| * | | ice40: Emit feed-through LUTs for PLL/LOCK | Sergiusz Bazanski | 2018-07-24 | 1 | -1/+1 |
| * | | ice40: Implement emitting PLLs | Sergiusz Bazanski | 2018-07-24 | 1 | -0/+41 |
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| * | Add Context::archcheck() and "nextpnr-ice40 --test" | Clifford Wolf | 2018-07-23 | 1 | -40/+54 |
| * | Bugfix in iCE40 chipdb.py | Clifford Wolf | 2018-07-23 | 1 | -3/+0 |
| * | Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 arch | Clifford Wolf | 2018-07-22 | 1 | -2/+27 |
| * | ice40: Add virtual padin wires for intoscs and GB_IOs | David Shah | 2018-07-19 | 1 | -1/+14 |
| * | ice40: Adding data for extra cell configuration | David Shah | 2018-07-19 | 1 | -3/+22 |
| * | Remove pip names from ice40 chip db to safe memory | Clifford Wolf | 2018-07-15 | 1 | -1/+1 |
| * | Add iCE40 Pip gfx | Clifford Wolf | 2018-07-15 | 1 | -6/+24 |
