| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Using hashlib in arches | gatecat | 2021-06-02 | 1 | -13/+10 |
| * | clangformat | gatecat | 2021-04-12 | 1 | -1/+1 |
| * | [interchange] Prevent site router from generating incorrect LUTs. | Keith Rothman | 2021-04-06 | 1 | -2/+4 |
| * | [interchange] Add crude pseudo pip model. | Keith Rothman | 2021-04-06 | 1 | -0/+10 |
| * | [interchange] Update to v6 of FPGA interchange chipdb. | Keith Rothman | 2021-04-01 | 1 | -0/+4 |
| * | Re-work LUT mapping logic to only put VCC pins when required. | Keith Rothman | 2021-03-25 | 1 | -0/+2 |
| * | Use NEXTPNR_NAMESPACE macro's now that headers are seperated. | Keith Rothman | 2021-03-15 | 1 | -2/+2 |
| * | Split nextpnr.h to allow for linear inclusion. | Keith Rothman | 2021-03-15 | 1 | -6/+8 |
| * | clangformat | gatecat | 2021-03-03 | 1 | -21/+20 |
| * | Initial LUT rotation logic. | Keith Rothman | 2021-02-26 | 1 | -0/+101 |
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index : iCE40/nextpnr | |
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