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path: root/fpga_interchange/luts.h
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* Using hashlib in archesgatecat2021-06-021-13/+10
* clangformatgatecat2021-04-121-1/+1
* [interchange] Prevent site router from generating incorrect LUTs.Keith Rothman2021-04-061-2/+4
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-061-0/+10
* [interchange] Update to v6 of FPGA interchange chipdb.Keith Rothman2021-04-011-0/+4
* Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-251-0/+2
* Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-151-2/+2
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-151-6/+8
* clangformatgatecat2021-03-031-21/+20
* Initial LUT rotation logic.Keith Rothman2021-02-261-0/+101